[SI-LIST] 回复： the relationship of tck(avg) and CL in DDR3 spec

  • From: John Lee <venussoso@xxxxxxxx>
  • To: "zheng.jackle@xxxxxxxxx" <zheng.jackle@xxxxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
  • Date: Thu, 23 May 2013 15:56:31 +0800 (CST)

Hi Jackle,
CL means Column Latency, because after the cell has been selected, the data 
needs some time to 'go to outside', this duration is defined by tck*CL.
For example, for 1600-11-11-11, the actual time is 1.25ns * 11 = 13.75ns.
This 13.75ns is DRAM's characteristic, it's almost the minimum requirement 
during actual operation. If you downgrade the frequency, the system will set 
the CL=9, 1.5 * 9 = 13.5ns.
 
Best Regards!
John Lee

________________________________
 发件人： jackle zheng <zheng.jackle@xxxxxxxxx>
收件人： si-list@xxxxxxxxxxxxx 
发送日期： 2013年5月23日, 星期四, 11:18 上午
主题: [SI-LIST] the relationship of tck(avg) and CL in DDR3 spec
 

hi, member,
I was testing my EP board on DDR3 compliance, my  tck(avg) was smaller than
spec. So, i checked the DDR3 spec, i found tck(avg) is correlated with CL
value. my question is what is the relationship of the two parameters???
any comment is appreciated.

-- 
我思故我在

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