[SI-LIST] Re: si-list Digest V5 #307
- From: "Russell Rapport" <rrapport@xxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Fri, 5 Aug 2005 14:08:12 -0500
=20
Russell Rapport
Senior Design Engineer II
Staktek
512-454-9531 x224 voice
512-454-9409 fax
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=20
-----Original Message-----
From: FreeLists Mailing List Manager [mailto:ecartis@xxxxxxxxxxxxx]=20
Sent: Friday, August 05, 2005 11:22 AM
To: si-list digest users
Subject: si-list Digest V5 #307
si-list Digest Fri, 05 Aug 2005 Volume: 05 Issue: 307
In This Issue:
#1: From: Darshan Mehta <darshanmehta2k@xxxxxxxxx>
Subject: [SI-LIST] Re: Return Path
#2: From: steve weir <weirsi@xxxxxxxxxx>
Subject: [SI-LIST] Re: Return Path
#3: From: Darshan Mehta <darshanmehta2k@xxxxxxxxx>
Subject: [SI-LIST] Re: Return Path
#4: From: Istvan Novak <istvan.novak@xxxxxxx>
Subject: [SI-LIST] Re: Return Path
#5: From: "Ken Cantrell" <Ken.Cantrell@xxxxxxxxxxxxxxxx>
Subject: [SI-LIST] Re: Package modeling tools
#6: From: "Ken Cantrell" <Ken.Cantrell@xxxxxxxxxxxxxxxx>
Subject: [SI-LIST] Re: ESD strips on board edge
#7: From: "Curt McNamara" <CurtM@xxxxxxxxxxx>
Subject: [SI-LIST] Re: ESD strips on board edge
#8: From: steve weir <weirsi@xxxxxxxxxx>
Subject: [SI-LIST] Re: ESD strips on board edge
----------------------------------------------------------------------
Msg: #1 in digest
Date: Fri, 5 Aug 2005 00:24:58 -0700 (PDT)
From: Darshan Mehta <darshanmehta2k@xxxxxxxxx>
Subject: [SI-LIST] Re: Return Path
Steve and Abhijit,
=20
Once again Thanks for clarifying my doubts.
=20
The formula for Capacitance calculation for Stripline configuration is
as follows (pF/inch);
=20
C =3D 1.4 * Er / ln [ 2.4 * (b / w)] =20
=20
Where b =3D total height of Dielectric between the Plane Layer and w is
the width of Trace.=20
=20
Generally we take the height between the Plane layers (return current
path) as the b in the capacitance calculation. But as per your mail if
the nearby conductors also act as a return current, what dielectric
height I should consider while calculating the Capacitance.
Thanks,
Darshan Mehta
=20
steve weir <weirsi@xxxxxxxxxx> wrote:
Darshan, Abhijit, I find Dr. Bogatin's book "Signal Integrity
Simplified"=20
is an excellent text that presents the material clearly without losing=20
technical accuracy. It belongs right up there with other excellent books
such as those by Dr. Johnson, Dally & Poulton, Young, and Hall. And I am
not just saying that because it features Teraspeed's development of
"Final=20
Inch" for Samtec.
Abhijit is correct. Any conductor is a better wave guide than=20
dielectric. Either provide conductors to supply the return path by=20
intention, or your signals will find other conductors on their own.
Steve.
At 11:53 PM 8/4/2005 -0700, Abhijit Mahajan wrote:
>Darshan
>
>Nearby signals traces can also act as return path. One possible way to
>improve return path situation (on two layer boards) is to use coplanar
>waveguide configuration. It can be useful for two layer boards having =
=3D
>high
>speed traces, and also when the board thickness is on the higher
side.=3D20
>
>BTW, I haven't read this book but it certainly sounds like a good one =
=3D
>since
>it got you thinking so much on return currents!
>
>Abhijit.
>=3D20
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx] =3D
>On
>Behalf Of Darshan Mehta
>Sent: Friday, August 05, 2005 11:35 AM
>To: steve weir; si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: Return Path
>
>Steve,
>
>=3D20
>
>Thanks for the reply.=3D20
>
>=3D20
>
>So you mean to say that if we don't have Plane Layer, the Electric and
>Magnetic field will be coupled to the nearby conductor. If we have a =
=3D
>Plane
>layer also present on the board, does the nearby conductor act as a =3D
>Return
>path? My basic question is, on what basis we should think that this =3D
>conductor
>will act as a return path for given signal. If the Plane shape is =3D
>present on
>the board, does the Plane as well as the nearby conductors will act as
a
>return current or only the Plane shape will act like return current =3D
>path.=3D20
>
>=3D20
>
>Thanks,
>
>Darshan Mehta
>
>
>steve weir wrote:
>Darshan, if you have a board with no dedicated plane, then the fields =
=3D
>will
>just spread out, coupling the signal into multiple conductors. A field
=3D
>solver
>can determine the coupling on each line for a given configuration.
>
>Steve.
>At 10:31 PM 8/4/2005 -0700, Darshan Mehta wrote:
> >Hello Experts,
> >
> >
> >
> >I have a question on return current. I was going through the =
book=3D20
> >"Signal Integrity Simplified" and came to know that return current
path =3D
>
> >can be a Power Plane or Ground Plane. I am still confused about
return=3D20
> >path. Let me describe what I understood.
> >
> >
> >
> >The Signal Path is the active path and the Electric field from
Signal=3D20
> >will terminate in the return path. The Magnetic field will form =
a=3D20
> >circular loop around the signal and it will be coupled with return
path =3D
>
> >so that equal and opposite current will flow in return path.
Normally=3D20
> >if we have Power Plane or Ground place, the return path will be easy
to =3D
>
> >find out. Let's assume, if we have a 2 layer board with no copper
shape =3D
>
> >drawn on it, how to find the return path for the signal? Please help
me
>understanding this.
> >
> >
> >
> >Thanks,
> >
> >Darshan Mehta
> >
> >
> >
> >
> >__________________________________________________
> >Do You Yahoo!?
> >Tired of spam? Yahoo! Mail has the best spam protection around=3D20
> >http://mail.yahoo.com
> >
> >------------------------------------------------------------------
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> >
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> >
>
>
>
>__________________________________________________
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>
>------------------------------------------------------------------
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>or at our remote archives:
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------------------------------
Msg: #2 in digest
Date: Fri, 05 Aug 2005 00:31:17 -0700
From: steve weir <weirsi@xxxxxxxxxx>
Subject: [SI-LIST] Re: Return Path
Darshan, please read Dr. Bogatin's book thoroughly. He demonstrates:
1. That all closed form formulas for wave guide impedance are=20
approximations with limited accuracy over finite ranges.
2. Line to line coupling for several configurations.
3. That to get a really accurate answer you need to use a field solver.
Steve.
At 12:24 AM 8/5/2005 -0700, Darshan Mehta wrote:
>Steve and Abhijit,<?xml:namespace prefix =3D o ns =3D=20
>"urn:schemas-microsoft-com:office:office" />
>
>
>
>Once again Thanks for clarifying my doubts.
>
>
>
>The formula for Capacitance calculation for Stripline configuration is
as=20
>follows (pF/inch);
>
>
>
>C =3D 1.4 * Er / ln [ 2.4 * (b / w)]
>
>
>
>Where b =3D total height of Dielectric between the Plane Layer and w is
the=20
>width of Trace.
>
>
>Generally we take the height between the Plane layers (return current=20
>path) as the b in the capacitance calculation. But as per your mail if
the=20
>nearby conductors also act as a return current, what dielectric height
I=20
>should consider while calculating the Capacitance.
>
>Thanks,
>
>Darshan Mehta
>
>
>
>
>steve weir <weirsi@xxxxxxxxxx> wrote:
>Darshan, Abhijit, I find Dr. Bogatin's book "Signal Integrity
Simplified"
>is an excellent text that presents the material clearly without losing
>technical accuracy. It belongs right up there with other excellent
books
>such as those by Dr. Johnson, Dally & Poulton, Young, and Hall. And I
am
>not just saying that because it features Teraspeed's development of
"Final
>Inch" for Samtec.
>
>Abhijit is correct. Any conductor is a better wave guide than
>dielectric. Either provide conductors to supply the return path by
>intention, or your signals will find other conductors on their own.
>
>Steve.
>At 11:53 PM 8/4/2005 -0700, Abhijit Mahajan wrote:
> >Darshan
> >
> >Nearby signals traces can also act as return path. One possible way
to
> >improve return path situation (on two layer boards) is to use
coplanar
> >waveguide configuration. It can be useful for two layer boards having
=3D
> >high
> >speed traces, and also when the board thickness is on the higher
side.=3D20
> >
> >BTW, I haven't read this book but it certainly sounds like a good one
=3D
> >since
> >it got you thinking so much on return currents!
> >
> >Abhijit.
> >=3D20
> >
> >-----Original Message-----
> >From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx] =3D
> >On
> >Behalf Of Darshan Mehta
> >Sent: Friday, August 05, 2005 11:35 AM
> >To: steve weir; si-list@xxxxxxxxxxxxx
> >Subject: [SI-LIST] Re: Return Path
> >
> >Steve,
> >
> >=3D20
> >
> >Thanks for the reply.=3D20
> >
> >=3D20
> >
> >So you mean to say that if we don't have Plane Layer, the Electric
and
> >Magnetic field will be coupled to the nearby conductor. If we have a
=3D
> >Plane
> >layer also present on the board, does the nearby conductor act as a =
=3D
> >Return
> >path? My basic question is, on what basis we should think that this =
=3D
> >conductor
> >will act as a return path for given signal. If the Plane shape is =3D
> >present on
> >the board, does the Plane as well as the nearby conductors will act
as a
> >return current or only the Plane shape will act like return current =
=3D
> >path.=3D20
> >
> >=3D20
> >
> >Thanks,
> >
> >Darshan Mehta
> >
> >
> >steve weir wrote:
> >Darshan, if you have a board with no dedicated plane, then the fields
=3D
> >will
> >just spread out, coupling the signal into multiple conductors. A
field =3D
> >solver
> >can determine the coupling on each line for a given configuration.
> >
> >Steve.
> >At 10:31 PM 8/4/2005 -0700, Darshan Mehta wrote:
> > >Hello Experts,
> > >
> > >
> > >
> > >I have a question on return current. I was going through the
book=3D20
> > >"Signal Integrity Simplified" and came to know that return current
path =3D
> >
> > >can be a Power Plane or Ground Plane. I am still confused about
return=3D20
> > >path. Let me describe what I understood.
> > >
> > >
> > >
> > >The Signal Path is the active path and the Electric field from
Signal=3D20
> > >will terminate in the return path. The Magnetic field will form
a=3D20
> > >circular loop around the signal and it will be coupled with return
path =3D
> >
> > >so that equal and opposite current will flow in return path.
Normally=3D20
> > >if we have Power Plane or Ground place, the return path will be
easy to =3D
> >
> > >find out. Let's assume, if we have a 2 layer board with no copper
shape =3D
> >
> > >drawn on it, how to find the return path for the signal? Please
help me
> >understanding this.
> > >
> > >
> > >
> > >Thanks,
> > >
> > >Darshan Mehta
> > >
> > >
> > >
> > >
> > >__________________________________________________
> > >Do You Yahoo!?
> > >Tired of spam? Yahoo! Mail has the best spam protection around=3D20
> > >http://mail.yahoo.com
> > >
> > >------------------------------------------------------------------
> > >To unsubscribe from si-list:
> > >si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject
field
> > >
> > >or to administer your membership from a web page, go to:
> > >//www.freelists.org/webpage/si-list
> > >
> > >For help:
> > >si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
> > >
> > >List FAQ wiki page is located at:
> > > http://si-list.org/wiki/wiki.pl?Si-List_FAQ
> > >
> > >List technical documents are available at:
> > > http://www.si-list.org
> > >
> > >List archives are viewable at:
> > > //www.freelists.org/archives/si-list
> > >or at our remote archives:
> > > http://groups.yahoo.com/group/si-list/messages
> > >Old (prior to June 6, 2001) list archives are viewable at:
> > > http://www.qsl.net/wb6tpu
> > >
> >
> >
> >
> >__________________________________________________
> >Do You Yahoo!?
> >Tired of spam? Yahoo! Mail has the best spam protection around
> >http://mail.yahoo.com=3D20
> >
> >------------------------------------------------------------------
> >To unsubscribe from si-list:
> >si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
> >
> >or to administer your membership from a web page, go to:
> >//www.freelists.org/webpage/si-list
> >
> >For help:
> >si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
> >
> >List FAQ wiki page is located at:
> > http://si-list.org/wiki/wiki.pl?Si-List_FAQ
> >
> >List technical documents are available at:
> > http://www.si-list.org
> >
> >List archives are viewable at: =3D20
> > //www.freelists.org/archives/si-list
> >or at our remote archives:
> > http://groups.yahoo.com/group/si-list/messages
> >Old (prior to June 6, 2001) list archives are viewable at:
> > http://www.qsl.net/wb6tpu
> > =3D20
> >
> >
> >
> >------------------------------------------------------------------
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> >
> >or to administer your membership from a web page, go to:
> >//www.freelists.org/webpage/si-list
> >
> >For help:
> >si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
> >
> >List FAQ wiki page is located at:
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> >
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> >
> >List archives are viewable at:
> > //www.freelists.org/archives/si-list
> >or at our remote archives:
> > http://groups.yahoo.com/group/si-list/messages
> >Old (prior to June 6, 2001) list archives are viewable at:
> > http://www.qsl.net/wb6tpu
> >
>
>
>
>__________________________________________________
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>Tired of spam? Yahoo! Mail has the best spam protection around
>http://mail.yahoo.com
------------------------------
Msg: #3 in digest
Date: Fri, 5 Aug 2005 01:07:38 -0700 (PDT)
From: Darshan Mehta <darshanmehta2k@xxxxxxxxx>
Subject: [SI-LIST] Re: Return Path
Steve,
=20
Now I understood why calculation does not give correct answer and field
solvers are used for Impedance calculation.
=20
Could you please tell me which book I should refer to know more about
"How the field Solver works", I am really keen to know about field
solvers.=20
=20
Thanks,
Darshan Mehta
steve weir <weirsi@xxxxxxxxxx> wrote:
Darshan, please read Dr. Bogatin's book thoroughly. He demonstrates:
1. That all closed form formulas for wave guide impedance are
approximations with limited accuracy over finite ranges.
2. Line to line coupling for several configurations.
3. That to get a really accurate answer you need to use a field solver.
Steve.
At 12:24 AM 8/5/2005 -0700, Darshan Mehta wrote:
Steve and Abhijit,<?xml:namespace prefix =3D o ns =3D
"urn:schemas-microsoft-com:office:office" />
=20
Once again Thanks for clarifying my doubts.
=20
The formula for Capacitance calculation for Stripline configuration is
as follows (pF/inch);
=20
C =3D 1.4 * Er / ln [ 2.4 * (b / w)] =20
=20
Where b =3D total height of Dielectric between the Plane Layer and w is
the width of Trace.=20
=20
Generally we take the height between the Plane layers (return current
path) as the b in the capacitance calculation. But as per your mail if
the nearby conductors also act as a return current, what dielectric
height I should consider while calculating the Capacitance.
Thanks,
Darshan Mehta
=20
steve weir <weirsi@xxxxxxxxxx> wrote:=20
Darshan, Abhijit, I find Dr. Bogatin's book "Signal Integrity
Simplified"=20
is an excellent text that presents the material clearly without
losing=20
technical accuracy. It belongs right up there with other excellent
books=20
such as those by Dr. Johnson, Dally & Poulton, Young, and Hall. And I
am=20
not just saying that because it features Teraspeed's development of
"Final=20
Inch" for Samtec.
Abhijit is correct. Any conductor is a better wave guide than=20
dielectric. Either provide conductors to supply the return path by=20
intention, or your signals will find other conductors on their own.
Steve.=20
At 11:53 PM 8/4/2005 -0700, Abhijit Mahajan wrote:=20
>Darshan=20
>=20
>Nearby signals traces can also act as return path. One possible way
to=20
>improve return path situation (on two layer boards) is to use
coplanar=20
>waveguide configuration. It can be useful for two layer boards
having =3D=20
>high=20
>speed traces, and also when the board thickness is on the higher
side.=3D20=20
>=20
>BTW, I haven't read this book but it certainly sounds like a good
one =3D=20
>since=20
>it got you thinking so much on return currents!=20
>=20
>Abhijit.=20
>=3D20=20
>=20
>-----Original Message-----=20
>From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx] =3D=20
>On=20
>Behalf Of Darshan Mehta=20
>Sent: Friday, August 05, 2005 11:35 AM=20
>To: steve weir; si-list@xxxxxxxxxxxxx=20
>Subject: [SI-LIST] Re: Return Path=20
>=20
>Steve,=20
>=20
>=3D20=20
>=20
>Thanks for the reply.=3D20=20
>=20
>=3D20=20
>=20
>So you mean to say that if we don't have Plane Layer, the Electric
and=20
>Magnetic field will be coupled to the nearby conductor. If we have a
=3D=20
>Plane=20
>layer also present on the board, does the nearby conductor act as a
=3D=20
>Return=20
>path? My basic question is, on what basis we should think that this
=3D=20
>conductor=20
>will act as a return path for given signal. If the Plane shape is =
=3D=20
>present on=20
>the board, does the Plane as well as the nearby conductors will act
as a=20
>return current or only the Plane shape will act like return current
=3D=20
>path.=3D20=20
>=20
>=3D20=20
>=20
>Thanks,=20
>=20
>Darshan Mehta=20
>=20
>=20
>steve weir wrote:=20
>Darshan, if you have a board with no dedicated plane, then the
fields =3D=20
>will=20
>just spread out, coupling the signal into multiple conductors. A
field =3D=20
>solver=20
>can determine the coupling on each line for a given configuration.=20
>=20
>Steve.=20
>At 10:31 PM 8/4/2005 -0700, Darshan Mehta wrote:=20
> >Hello Experts,=20
> >=20
> >=20
> >=20
> >I have a question on return current. I was going through the
book=3D20=20
> >"Signal Integrity Simplified" and came to know that return current
path =3D=20
>=20
> >can be a Power Plane or Ground Plane. I am still confused about
return=3D20=20
> >path. Let me describe what I understood.=20
> >=20
> >=20
> >=20
> >The Signal Path is the active path and the Electric field from
Signal=3D20=20
> >will terminate in the return path. The Magnetic field will form
a=3D20=20
> >circular loop around the signal and it will be coupled with return
path =3D=20
>=20
> >so that equal and opposite current will flow in return path.
Normally=3D20=20
> >if we have Power Plane or Ground place, the return path will be
easy to =3D=20
>=20
> >find out. Let's assume, if we have a 2 layer board with no copper
shape =3D=20
>=20
> >drawn on it, how to find the return path for the signal? Please
help me=20
>understanding this.=20
> >=20
> >=20
> >=20
> >Thanks,=20
> >=20
> >Darshan Mehta=20
> >=20
> >=20
> >=20
> >=20
> >__________________________________________________=20
> >Do You Yahoo!?=20
> >Tired of spam? Yahoo! Mail has the best spam protection =
around=3D20=20
> >http://mail.yahoo.com=20
> >=20
> >------------------------------------------------------------------
> >To unsubscribe from si-list:=20
> >si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject
field=20
> >=20
> >or to administer your membership from a web page, go to:=20
> >//www.freelists.org/webpage/si-list=20
> >=20
> >For help:=20
> >si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field=20
> >=20
> >List FAQ wiki page is located at:=20
> > http://si-list.org/wiki/wiki.pl?Si-List_FAQ=20
> >=20
> >List technical documents are available at:=20
> > http://www.si-list.org=20
> >=20
> >List archives are viewable at:=20
> > //www.freelists.org/archives/si-list=20
> >or at our remote archives:=20
> > http://groups.yahoo.com/group/si-list/messages=20
> >Old (prior to June 6, 2001) list archives are viewable at:=20
> > http://www.qsl.net/wb6tpu=20
> >=20
>=20
>=20
>=20
>__________________________________________________=20
>Do You Yahoo!?=20
>Tired of spam? Yahoo! Mail has the best spam protection around=20
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------------------------------
Msg: #4 in digest
Date: Fri, 05 Aug 2005 08:38:09 -0400
From: Istvan Novak <istvan.novak@xxxxxxx>
Subject: [SI-LIST] Re: Return Path
Darshan,
An excellent book on field solvers is:
Daniel Swanson, Wolfgang Hoefer: Microwave Circuit Modeling using=20
Electromagnetic Field Simulation. Artech House, 2003.
Regards,
Istvan Novak
SUN Microsystems
Darshan Mehta wrote:
>Steve,
>
>=20
>
>Now I understood why calculation does not give correct answer and field
solvers are used for Impedance calculation.
>
>=20
>
>Could you please tell me which book I should refer to know more about
"How the field Solver works", I am really keen to know about field
solvers.=20
>
>=20
>
>Thanks,
>
>Darshan Mehta
>
>
>steve weir <weirsi@xxxxxxxxxx> wrote:
>Darshan, please read Dr. Bogatin's book thoroughly. He demonstrates:
>
>1. That all closed form formulas for wave guide impedance are
approximations with limited accuracy over finite ranges.
>2. Line to line coupling for several configurations.
>3. That to get a really accurate answer you need to use a field solver.
>
>Steve.
>At 12:24 AM 8/5/2005 -0700, Darshan Mehta wrote:
>
>Steve and Abhijit,<?xml:namespace prefix =3D o ns =3D
"urn:schemas-microsoft-com:office:office" />
>
>=20
>
>Once again Thanks for clarifying my doubts.
>
>=20
>
>The formula for Capacitance calculation for Stripline configuration is
as follows (pF/inch);
>
>=20
>
>C =3D 1.4 * Er / ln [ 2.4 * (b / w)] =20
>
>=20
>
>Where b =3D total height of Dielectric between the Plane Layer and w is
the width of Trace.=20
>
>=20
>Generally we take the height between the Plane layers (return current
path) as the b in the capacitance calculation. But as per your mail if
the nearby conductors also act as a return current, what dielectric
height I should consider while calculating the Capacitance.
>
>Thanks,
>
>Darshan Mehta
>
>=20
>
>
>steve weir <weirsi@xxxxxxxxxx> wrote:=20
> Darshan, Abhijit, I find Dr. Bogatin's book "Signal Integrity
Simplified"=20
> is an excellent text that presents the material clearly without
losing=20
> technical accuracy. It belongs right up there with other excellent
books=20
> such as those by Dr. Johnson, Dally & Poulton, Young, and Hall. And
I am=20
> not just saying that because it features Teraspeed's development of
"Final=20
> Inch" for Samtec.
>
>
> Abhijit is correct. Any conductor is a better wave guide than=20
> dielectric. Either provide conductors to supply the return path by=20
> intention, or your signals will find other conductors on their own.
>
>
> Steve.=20
> At 11:53 PM 8/4/2005 -0700, Abhijit Mahajan wrote:=20
> >Darshan=20
> >=20
> >Nearby signals traces can also act as return path. One possible way
to=20
> >improve return path situation (on two layer boards) is to use
coplanar=20
> >waveguide configuration. It can be useful for two layer boards
having =3D=20
> >high=20
> >speed traces, and also when the board thickness is on the higher
side.=3D20=20
> >=20
> >BTW, I haven't read this book but it certainly sounds like a good
one =3D=20
> >since=20
> >it got you thinking so much on return currents!=20
> >=20
> >Abhijit.=20
> >=3D20=20
> >=20
> >-----Original Message-----=20
> >From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx] =3D=20
> >On=20
> >Behalf Of Darshan Mehta=20
> >Sent: Friday, August 05, 2005 11:35 AM=20
> >To: steve weir; si-list@xxxxxxxxxxxxx=20
> >Subject: [SI-LIST] Re: Return Path=20
> >=20
> >Steve,=20
> >=20
> >=3D20=20
> >=20
> >Thanks for the reply.=3D20=20
> >=20
> >=3D20=20
> >=20
> >So you mean to say that if we don't have Plane Layer, the Electric
and=20
> >Magnetic field will be coupled to the nearby conductor. If we have
a =3D=20
> >Plane=20
> >layer also present on the board, does the nearby conductor act as a
=3D=20
> >Return=20
> >path? My basic question is, on what basis we should think that this
=3D=20
> >conductor=20
> >will act as a return path for given signal. If the Plane shape is =
=3D
> >present on=20
> >the board, does the Plane as well as the nearby conductors will act
as a=20
> >return current or only the Plane shape will act like return current
=3D=20
> >path.=3D20=20
> >=20
> >=3D20=20
> >=20
> >Thanks,=20
> >=20
> >Darshan Mehta=20
> >=20
> >=20
> >steve weir wrote:=20
> >Darshan, if you have a board with no dedicated plane, then the
fields =3D=20
> >will=20
> >just spread out, coupling the signal into multiple conductors. A
field =3D=20
> >solver=20
> >can determine the coupling on each line for a given configuration.=20
> >=20
> >Steve.=20
> >At 10:31 PM 8/4/2005 -0700, Darshan Mehta wrote:=20
> > >Hello Experts,=20
> > >=20
> > >=20
> > >=20
> > >I have a question on return current. I was going through the
book=3D20=20
> > >"Signal Integrity Simplified" and came to know that return
current path =3D=20
> >=20
> > >can be a Power Plane or Ground Plane. I am still confused about
return=3D20=20
> > >path. Let me describe what I understood.=20
> > >=20
> > >=20
> > >=20
> > >The Signal Path is the active path and the Electric field from
Signal=3D20=20
> > >will terminate in the return path. The Magnetic field will form
a=3D20=20
> > >circular loop around the signal and it will be coupled with
return path =3D=20
> >=20
> > >so that equal and opposite current will flow in return path.
Normally=3D20=20
> > >if we have Power Plane or Ground place, the return path will be
easy to =3D=20
> >=20
> > >find out. Let's assume, if we have a 2 layer board with no copper
shape =3D=20
> >=20
> > >drawn on it, how to find the return path for the signal? Please
help me=20
> >understanding this.=20
> > >=20
> > >=20
> > >=20
> > >Thanks,=20
> > >=20
> > >Darshan Mehta=20
> > >=20
> =20
>
------------------------------
Msg: #5 in digest
From: "Ken Cantrell" <Ken.Cantrell@xxxxxxxxxxxxxxxx>
Subject: [SI-LIST] Re: Package modeling tools
Date: Fri, 5 Aug 2005 07:51:40 -0600
Ambr -
Search the SI list archives. Lots of information on this subject.
Ken
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Ambr Amit
Sent: Thursday, August 04, 2005 7:50 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Package modeling tools
Hi Gurus,
Anyone has comments/data on following queries?
I'm working in India office of Texas Instruments
and would really appreciate your help in this.
Thanks,
Amit
--- Ambr Amit <ambr_amit@xxxxxxxxx> wrote:
> Hello Gurus,
> I would like to know if anyone has comparison
> data
> for the following tools (comparison for/with other
> tools are also welcome):
>
> - PakSi (Optimal)
> - PowerSI (Sigrity)
> - Icemax (Fluent)
>
> We are also doing comparison for these tools but
> have not reached any conclusion and would appreciate
> any help from you all. We are looking at following
> things in terms of comparison:
>
> - working capabilities of the tools (not the
> capabilities given in marketing presentation)
> - accuracy
> - run time
> - advantages/disadvantages
> - issues
>
> PS: AEs for the respective tools, please refrain
> from
> replying to this mail. I want to get info from the
> real users of the tools and not developers.
>
> Thanks,
> Amit
>
>
>
> ____________________________________________________
> Start your day with Yahoo! - make it your home page
> http://www.yahoo.com/r/hs
>
>
____________________________________________________
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------------------------------
Msg: #6 in digest
From: "Ken Cantrell" <Ken.Cantrell@xxxxxxxxxxxxxxxx>
Subject: [SI-LIST] Re: ESD strips on board edge
Date: Fri, 5 Aug 2005 07:56:23 -0600
Another simple thing to do (for plastic hand-held units) is metallize
the
inside, and tongue-and-groove the mating halves. This keeps a lot of
the
events from entering the enclosure in the first place.
Ken
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Curt McNamara
Sent: Thursday, August 04, 2005 9:41 AM
To: weirsi@xxxxxxxxxx; davidjp@xxxxxxx; koh-yew.thoon@xxxxxx; SI-List
Subject: [SI-LIST] Re: ESD strips on board edge
I think the first place I saw ESD strips mentioned in print was Henry
Ott's
_Noise Reduction Techniques in Electronic Systems_ Here are a couple of
things
we do:
Cut the planes back from the board edge so the ESD strip is the first
piece
of metal that an ESD event could couple to.
Put ESD strips on top and bottom and tie them together with vias
regularly
(1cm or so).=3D20
Connect the ESD strip to the "RF Ground". This will be the largest piece
of=3D20
metal that energy could couple to. It may or may not be your circuit
ground!
If it *is* your circuit ground make this connection in a place where
energy cannot
travel across the plane and damage devices.
Curt
Curt McNamara. P.E.=3D20
Senior Electrical Engineer=3D20
Logic Product Development=3D20
411 Washington Ave. N Suite 101=3D20
Minneapolis, MN 55401=3D20
Tel 612-436-5178=3D20
Fax 612-672-0443=3D20
curtm@xxxxxxxxxxx=3D20
www.logicpd.com=3D20
This message (including any attachments) contains confidential
information intended for a specific individual and purpose, and is
protected by law. If you are not the intended recipient, you should
delete this message and are hereby notified that any disclosure,
copying, or distribution of this message, or the taking of any action
based on it, is strictly prohibited.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of steve weir
Sent: Thursday, August 04, 2005 10:19 AM
To: davidjp@xxxxxxx; koh-yew.thoon@xxxxxx; SI-List
Subject: [SI-LIST] Re: ESD strips on board edge
Dr. Pommerenke, one additional note: It is important to maintain=3D20
dielectric sufficient separation between an ESD strip and any other
PCB=3D20
features so that a secondary arc doesn't bypass the ferrite. =
Surface=3D20
contamination can be a problem.
Regards,
Steve.
At 10:01 AM 8/4/2005 -0500, Pommerenke, David wrote:
>Koh,
>
>In general, those strips are placed as landing area for sparks that hit
>the edge of the board. Sparks can hit the edge of the board in two-part
>plastic enclosures or during handling. However, during handling
other=3D20
>parts can be hit to.
>
>If you are working with a two-piece plastic enclosure, then it might be
>a good idea to have an ESD strip on the board edge. The strip should be
>connected to your "ground". I suggest to avoid a direct connection, but
>to use a ferrite bead (e.g., 300 Ohm at 100MHz). The bead will
survive=3D20
>the ESD current, but it reduces the current amplitude and increases the
>rise time. The fact that it will go into saturation is not that=3D20
>critical, tests have shown that it stays somewhat efficient in reducing
>the current peak amplitude and increasing the rise time. A =
resistor=3D20
>(e.g., 1000 Ohm) would be an alternative, but most resistors will =
be=3D20
>destroyed by the ESD current.
>
>Dr. David Pommerenke
>EMC laboratory
>University Missouri Rolla
>www.emclab.umr.edu
>
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx=3D20
>[mailto:si-list-bounce@xxxxxxxxxxxxx]
>On Behalf Of Thoon, Koh Yew
>Sent: Thursday, August 04, 2005 1:13 AM
>To: SI-List
>Subject: [SI-LIST] ESD strips on board edge
>
>=3D3D3D20
>Hi folks,=3D3D3D20
>
>I wonder if there's any good documents on implemenation of ESD
strips=3D20
>for Board edge.
>
>Thanks
>------------------------------------------------------------------
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>
>or to administer your membership from a web page, go to:=3D20
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>
>
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------------------------------
Msg: #7 in digest
Subject: [SI-LIST] Re: ESD strips on board edge
Date: Fri, 5 Aug 2005 08:58:53 -0500
From: "Curt McNamara" <CurtM@xxxxxxxxxxx>
Doug Smith said:
>Beware of static charge building up on this path when the board is
not=3D20
>in a system by charge induction by nearby charges. This can create =
a=3D20
>destructive ESD event where there would have been none except for
the=3D20
>presence of the ESD ring unless there is a conducting path between
the=3D20
>board and the ring.
An excellent point and shows the need to examine configurations. In the
cases I talked about the board was installed in its package or
connector.
In this case, with the guard ring located where ESD could enter, and the
guard ring is coupled to metal in a way that does not conduct energy
through circuitry, then it is useful.
For a board assembly not connected into a package or connector we assume
that for some distance it will be transported by hand through air.
Most=3D20
all add-in boards recommend (and some even include) guard straps to make
sure the installer does not have a static charge build-up.
There are many cases where these assumptions about installation break
down
-- we are building a large instrument rack for a customer where =
trays=3D20
get installed by hand with test devices on them. A number of precautions
have been taken to ensure no charge is accumulated on the tray as it is
transported and inserted. Still, the devices internal to the tray have
circuit elements which terminate in a connector. Since we can't ensure
that no charge exists on these traces we have treated every line =
with=3D20
ESD protection devices.
Curt
Curt McNamara. P.E.=3D20
Senior Electrical Engineer=3D20
Logic Product Development=3D20
411 Washington Ave. N Suite 101=3D20
Minneapolis, MN 55401=3D20
Tel 612-436-5178=3D20
Fax 612-672-0443=3D20
curtm@xxxxxxxxxxx=3D20
www.logicpd.com=3D20
This message (including any attachments) contains confidential
information intended for a specific individual and purpose, and is
protected by law. If you are not the intended recipient, you should
delete this message and are hereby notified that any disclosure,
copying, or distribution of this message, or the taking of any action
based on it, is strictly prohibited.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Doug Smith
Sent: Thursday, August 04, 2005 1:01 PM
To: koh-yew.thoon@xxxxxx
Cc: SI-List
Subject: [SI-LIST] Re: ESD strips on board edge
Hi Koh,
You could title this subject "The Board of the Rings."
If you mean ESD guard rings, this topic is worth several pages of=3D20
typing, actually a whole chapter in a book. These often make things=3D20
worse under a number of conditions. Keep in mind the voltage drop=3D20
along one of these paths during ESD events can be hundreds of volts
or=3D20
more from Ldi/dt drop and this gets into other paths my Mdi/dt.
Never connect an ESD guard ring through the board connector to
ground.=3D20
It just deposits the ESD energy right into your backplane (whether
you=3D20
think you connected it to "chassis" ground or not. A hundred volts=3D20
induce in series with nearby connector pins would not surprise me.
Beware of static charge building up on this path when the board is
not=3D20
in a system by charge induction by nearby charges. This can create =
a=3D20
destructive ESD event where there would have been none except for =
the=3D20
presence of the ESD ring unless there is a conducting path between
the=3D20
board and the ring.
I have barely touched the surface of this topic. If you want to =
call=3D20
me on the phone, I can eliminate lots of typing.
Doug
Thoon, Koh Yew wrote:
> =3D3D20
> Hi folks,=3D3D20
>=3D20
> I wonder if there's any good documents on implemenation of ESD
strips=3D20
> for Board edge.
>=3D20
> Thanks
> ------------------------------------------------------------------
> To unsubscribe from si-list:
> si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
>=3D20
> or to administer your membership from a web page, go to:=3D20
> //www.freelists.org/webpage/si-list
>=3D20
> For help:
> si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
>=3D20
> List FAQ wiki page is located at:
> http://si-list.org/wiki/wiki.pl?Si-List_FAQ
>=3D20
> List technical documents are available at:
> http://www.si-list.org
>=3D20
> List archives are viewable at: =3D20
> //www.freelists.org/archives/si-list
> or at our remote archives:
> http://groups.yahoo.com/group/si-list/messages
> Old (prior to June 6, 2001) list archives are viewable at:
> http://www.qsl.net/wb6tpu
> =3D20
>=3D20
>=3D20
>=3D20
--=3D20
-------------------------------------------------------
___ _ Doug Smith
\ / ) P.O. Box 1457
=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D Los Gatos, =
CA 95031-1457
_ / \ / \ _ TEL/FAX: 408-356-4186/358-3799
/ /\ \ ] / /\ \ Mobile: 408-858-4528
| q-----( ) | o | Email: doug@xxxxxxxxxx
\ _ / ] \ _ / Website: http://www.dsmith.org
-------------------------------------------------------
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------------------------------
Msg: #8 in digest
Date: Fri, 05 Aug 2005 09:19:44 -0700
From: steve weir <weirsi@xxxxxxxxxx>
Subject: [SI-LIST] Re: ESD strips on board edge
Ken, I prefer carbon coatings, but the principle is the same.
Steve
At 07:56 AM 8/5/2005 -0600, Ken Cantrell wrote:
>Another simple thing to do (for plastic hand-held units) is metallize
the
>inside, and tongue-and-groove the mating halves. This keeps a lot of
the
>events from entering the enclosure in the first place.
>Ken
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx
>[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Curt McNamara
>Sent: Thursday, August 04, 2005 9:41 AM
>To: weirsi@xxxxxxxxxx; davidjp@xxxxxxx; koh-yew.thoon@xxxxxx; SI-List
>Subject: [SI-LIST] Re: ESD strips on board edge
>
>
>I think the first place I saw ESD strips mentioned in print was Henry
>Ott's
>_Noise Reduction Techniques in Electronic Systems_ Here are a couple of
>things
>we do:
>
>Cut the planes back from the board edge so the ESD strip is the first
>piece
>of metal that an ESD event could couple to.
>
>Put ESD strips on top and bottom and tie them together with vias
>regularly
>(1cm or so).=3D20
>
>Connect the ESD strip to the "RF Ground". This will be the largest
piece
>of=3D20
>metal that energy could couple to. It may or may not be your circuit
>ground!
>If it *is* your circuit ground make this connection in a place where
>energy cannot
>travel across the plane and damage devices.
>
> Curt
>
>Curt McNamara. P.E.=3D20
>Senior Electrical Engineer=3D20
>Logic Product Development=3D20
>411 Washington Ave. N Suite 101=3D20
>Minneapolis, MN 55401=3D20
>Tel 612-436-5178=3D20
>Fax 612-672-0443=3D20
>curtm@xxxxxxxxxxx=3D20
>www.logicpd.com=3D20
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>
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
>On Behalf Of steve weir
>Sent: Thursday, August 04, 2005 10:19 AM
>To: davidjp@xxxxxxx; koh-yew.thoon@xxxxxx; SI-List
>Subject: [SI-LIST] Re: ESD strips on board edge
>
>
>Dr. Pommerenke, one additional note: It is important to maintain=3D20
>dielectric sufficient separation between an ESD strip and any other
PCB=3D20
>features so that a secondary arc doesn't bypass the ferrite.
Surface=3D20
>contamination can be a problem.
>
>Regards,
>
>
>Steve.
>
>
>At 10:01 AM 8/4/2005 -0500, Pommerenke, David wrote:
> >Koh,
> >
> >In general, those strips are placed as landing area for sparks that
hit
>
> >the edge of the board. Sparks can hit the edge of the board in
two-part
>
> >plastic enclosures or during handling. However, during handling
other=3D20
> >parts can be hit to.
> >
> >If you are working with a two-piece plastic enclosure, then it might
be
>
> >a good idea to have an ESD strip on the board edge. The strip should
be
>
> >connected to your "ground". I suggest to avoid a direct connection,
but
>
> >to use a ferrite bead (e.g., 300 Ohm at 100MHz). The bead will
survive=3D20
> >the ESD current, but it reduces the current amplitude and increases
the
>
> >rise time. The fact that it will go into saturation is not that=3D20
> >critical, tests have shown that it stays somewhat efficient in
reducing
>
> >the current peak amplitude and increasing the rise time. A
resistor=3D20
> >(e.g., 1000 Ohm) would be an alternative, but most resistors will
be=3D20
> >destroyed by the ESD current.
> >
> >Dr. David Pommerenke
> >EMC laboratory
> >University Missouri Rolla
> >www.emclab.umr.edu
> >
> >
> >-----Original Message-----
> >From: si-list-bounce@xxxxxxxxxxxxx=3D20
> >[mailto:si-list-bounce@xxxxxxxxxxxxx]
> >On Behalf Of Thoon, Koh Yew
> >Sent: Thursday, August 04, 2005 1:13 AM
> >To: SI-List
> >Subject: [SI-LIST] ESD strips on board edge
> >
> >=3D3D3D20
> >Hi folks,=3D3D3D20
> >
> >I wonder if there's any good documents on implemenation of ESD
strips=3D20
> >for Board edge.
> >
> >Thanks
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