Yes, clock jitter is hypersensitive so we often use it for measuring Powe rail
noise, even as low as uV.
I've done an article, EDICON paper and webinar, all titled something like
"Designing Power for Sensitive Circuits"
Well done Iliya!
From: FreeLists Mailing List Manager
Sent: Thursday, August 30, 10:08 PM
Subject: si-list Digest V18 #300
To: si-list digest users
si-list Digest Thu, 30 Aug 2018 Volume: 18 Issue: 300 In This Issue:
#1: From: "Iliya Zamek" (Redacted sender "i_zamek" Subject:
[SI-LIST] Re: Controlled ESR capacitor #2: From: "Cheng, Chris"
Subject: [SI-LIST] Re: Controlled ESR capacitor
---------------------------------------------------------------------- Msg: #1
in digest Date: Thu, 30 Aug 2018 06:48:40 +0000 (UTC) From: "Iliya Zamek"
(Redacted sender "i_zamek" Subject: [SI-LIST] Re: Controlled ESR capacitor Hi
Chris,ÃÂ Sorry for the late reply; I was busy after work tonight.ÃÂ Thank you
for reading my paper "On-chip Jitter and system Power Integrity" DesignCon
2012. You are still having in mind a design and how we can improve it, but this
is not a case. This paper main goals were:ÃÂ 1) to describe the method for PDN
validation through Jitter measurements which less impacted by parasitic and
applicable for any ICs weather they have special features, or not, that other
methods require;ÃÂ 2) using this method we revealed Jitter resonance induced
by PDN noise that origin of switching on-die logic.ÃÂ ÃÂ ÃÂ Note, that
this is a characteristic of PDN performance "looking from the die side".3)
next, using this method we researched how on-board decoupling impacts the PDN
resonances.ÃÂ ÃÂ The method: two logic domains in standard FPGA were used
that share the same PDN; one logic domain was used as an Aggressor, and other
as a Victim. Both were switching periodically and asynchronously. Switching
frequency sequentially changing and Jitter of a Victim was each time
measured.ÃÂ Jitter resonance: switching of an aggressorÃÂ createsÃÂ pulses
of a current corresponding each rise and fall time of Aggressor signal; these
current pulses causes PDN voltage variations (noise). Changing Aggressor
frequency we change noise frequency; when noise frequency reaches PDN resonance
the impact on the Victim became higher and victim Jitter reaches the peak. So,
this is a way to find a PDN resonances.ÃÂ ÃÂ ÃÂ Decoupling: we changed
on-board decoupling and measured Jitter; we obtained that with rising
decoupling at 36 MHz the resonance became stronger and in field 100-200 MHz
Jitter slightly reduced - this effect also explained in paragraph following the
graph. These measurements are time consum ing and we did not measure higher
resonances. I think that Jitter reduction at 100-200 MHz with increasing
decoupling is an evidence that higher frequency resonances also became more
narrow and higher.ÃÂ ÃÂ ÃÂ So, we did not sacrifice nothing; we just did
an experiment, got data, and explained the effects.ÃÂ I was glad to see
Binayak' good explanation of the effect that I also got from these experiments:
looking from die capacitance through package inductance to the decoupling we
see parallel resonance. Its' ESR is decreasing with rising number of the
capacitances. When ESR is decreased, Q-factor rising and, also, the resonance
peak.ÃÂ ÃÂ ÃÂ Chris,ÃÂ I agree with you that these results are important
as an illustration of new effects that has not been noted before: particular,
it was demonstrated that the traditional approachto the reducing PDN resonances
by increasing the decoupling on PCB does not help toremove resonance peaks.
Otherwise,lowering the PCB impedance by adding more capacitances makes the
situation evenworse, - the values of the peaks increase. I will be glad to
continue this discussion, which is very interesting for me personally. However
might be not all Si-listers are interested in it;ÃÂ should we move it
off-line? Best regards,ÃÂ IliyaÃÂ ÃÂ On Wednesday, August 29, 2018, 4:59:50
PM PDT, Cheng, Chris wrote: Your clarification makes me even more puzzled about
your conclusions. If this is general one die core noise to clock tree buffer
power, why would you sacrifice the critical >100MHz noise damping that most
core logic will care for the 30MHz or so that most switching logic don't care ?
Is your chip only working in 30-40MHz ? Back to the PLL jitter issue. As long
as the clock buffer output is used for the PLL phase detector input, it is
still part of the closed PLL controlled loop. You can see below 20MHz the PLL
loop bandwidth corrected the induced jitter on the clock tree buffer. You just
luck out that when the reduced cap configuration peaked around 10MHz, that was
below the PLL loop bandwidth. Had the PLL loop bandwidth is forced to be
lowered by crazy PLL spec like PCIE to 5MHz, the 10MHz peaking of the red curve
will most probably be higher than the high cap count configuration peak around
35MHz.ÃÂ Sorry, these are important design trade-offs that I am not sure you
have drawn the right conclusion. We should keep this discussion going. Chris
Cheng Distinguished Technologist , Electrical Hewlett-Packard Enterprise
Company ÃÂ +1 510 344 4439/ TelÃÂ chris.cheng@xxxxxxxÃÂ / EmailÃÂ 940 N.
McCarthy Blvd., Milpitas, CA 95035 USA From: Iliya Zamek
[mailto:i_zamek@xxxxxxxxx]ÃÂ Sent: Wednesday, August 29, 2018 1:28 PM To: ;
Cheng, Chris Cc:ÃÂ dmarc-noreply@xxxxxxxxxxxxx;ÃÂ binayaks@xxxxxxxxxÃÂ ;ÃÂ
tom@xxxxxxxxxxxxxxxxx;ÃÂ si-list@xxxxxxxxxxxxxÃÂ ; FRED MOTTER ; FRED B ;
Jacques Tazartes ; EmadIbrahim ;ÃÂ Myrna5@xxxxxxxxxxxxxxÃÂ ; Istvan Novak
;ÃÂ junichi.yamada.ak@xxxxxxxxxxxÃÂ ; Cosmin Iorga Subject: Re: [SI-LIST] Re:
Controlled ESR capacitor Hi Chris, Thank you for your comments.ÃÂ Both, 30-40
and 100-200 MHz jitterÃÂ components are important. There is noÃÂ point to
sacrifice one, or other.ÃÂ This was special experiment to validateÃÂ ÃÂ
the role of board decoupling onÃÂ interaction of two logic domains insideÃÂ
the chip which shared the sameÃÂ power supply: core logic was switchingÃÂ
(Aggressor) impacting routingÃÂ component's and clock tree' jitter
(victims).ÃÂ ÃÂ PLL on clock tree was using other, quietÃÂ power
supply.ÃÂ Scale is the same as onÃÂ figure 4: (jitter at core
switching)/(jitterÃÂ at core quiet). Let me know if you have more questions.
Thank you. Iliya On Aug 29, 2018 11:10 AM, "Cheng, Chris" wrote: Why do you
think it is worth sacrificing the 100-200MHz jitter performance with high cap
count for the narrow range of 30-40MHz jitter performance with lower cap count
?ÃÂ In the world of XbitY coding for the 10+Gb/s world, I would think the
100-200Mhz jitter performance is much more important than those 30-40MHz.ÃÂ
To me, the best conclusion I can draw from the two graph seems to point out the
price we pay for the obsession of jitter transfer over jitter accumulation.
Clearly the 30-40Mhz jitter peaking could be fixed by uping the PLL loop
bandwidth from around 10MHz to 40+MHz. In the name of saving a few $ in cheap
clock source, we paid this price for all PLL jitter accumulation downstream.ÃÂ
To recap :ÃÂ a) Who would feed a PLL with raw unfiltered power and rely on
decoupling cap ESR to maintain PLL jitter performance ?ÃÂ b) Why is it worth
sacrificing 100-200MHz jitter performance to a lower band 30-40MHz ?ÃÂ Also,
what was the vertical scale of the graphs ?ÃÂ Chris ChengÃÂ Distinguished
Technologist , ElectricalÃÂ Hewlett-Packard Enterprise CompanyÃÂ ÃÂ ÃÂ
+1 510 344 4439/ TelÃÂ chris.cheng@xxxxxxxÃÂ / EmailÃÂ 940 N. McCarthy
Blvd., Milpitas, CA 95035ÃÂ USAÃÂ -----Original Message-----ÃÂ From:ÃÂ
si-list-bounce@xxxxxxxxxxxxxÃÂ [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf ;
Of Iliya ZamekÃÂ Sent: Monday, August 27, 2018 8:39 PMÃÂ To:ÃÂ
binayaks@xxxxxxxxxÃÂ Cc:ÃÂ dmarc-noreply@xxxxxxxxxxxxx; Cheng, Chris ;ÃÂ
tom@xxxxxxxxxxxxxxxxx;ÃÂ si-list@xxxxxxxxxxxxx; FRED MOTTER ; FRED B ; Jacques
Tazartes ; EmadIbrahim ;ÃÂ Myrna5@xxxxxxxxxxxxxx; Istvan Novak ;ÃÂ
junichi.yamada.ak@xxxxxxxxxxx; Cosmin Iorga ÃÂ Subject: [SI-LIST] Re:
Controlled ESR capacitorÃÂ Somehow my email was distorted. Re-sending.ÃÂ ÃÂ
Hi Binayak,ÃÂ Your effect description is correct.ÃÂ If you look at papers
which links were included in my email sent 2 days ago (August 25) you can see
the graphÃâ that described exactly the same - how low PCB impedance causes
rising on-die transients.ÃÂ If you could not find these papers, you might
connect me off-line and I'll send it to you.ÃÂ Thank you.ÃÂ Iliya.ÃÂ
intensive on-board decoupling does not reduce PDN resonances respect to the
chip die, but even make PDN performance worse, - resonances are rising.ÃÂ I
will be glad to continue this discussion, however might be not all Si-listers
are interested in it and we should move it off-line? Best regards,ÃÂ IliyaÃÂ
ÃÂ On Wednesday, August 29, 2018, 4:59:50 PM PDT, Cheng, Chris wrote: Your
clarification makes me even more puzzled about your conclusions. If this is
general one die core noise to clock tree buffer power, why would you sacrifice
the critical >100MHz noise damping that most core logic will care for the 30MHz
or so that most switching logic don't care ? Is your chip only working in
30-40MHz ? Back to the PLL jitter issue. As long as the clock buffer output is
used for the PLL phase detector input, it is still part of the closed PLL
controlled loop. You can see below 20MHz the PLL loop bandwidth corrected the
induced jitter on the clock tree buffer. You just luck out that when the
reduced cap configuration peaked around 10MHz, that was below the PLL loop
bandwidth. Had the PLL loop bandwidth is forced to be lowered by crazy PLL spec
like PCIE to 5MHz, the 10MHz peaking of the red curve will most probably be
higher than the high cap count configuration peak around 35MHz. Sorry, these
are important design trade-offs that I am not sure you have drawn the right
conclusion. We should keep this discussion going. Chris Cheng Distinguished
Technologist , Electrical Hewlett-Packard Enterprise Company ÃÂ +1 510 344
4439/ Tel chris.cheng@xxxxxxx / Email 940 N. McCarthy Blvd., Milpitas, CA 95035
USA From: Iliya Zamek [mailto:i_zamek@xxxxxxxxx] Sent: Wednesday, August 29, ;
2018 1:28 PM To: Cheng, Chris Cc: dmarc-noreply@xxxxxxxxxxxxx;
binayaks@xxxxxxxxx ; tom@xxxxxxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx ; FRED MOTTER
; FRED B ; Jacques Tazartes ; EmadIbrahim ; Myrna5@xxxxxxxxxxxxxx ; Istvan
Novak ; junichi.yamada.ak@xxxxxxxxxxx ; Cosmin Iorga Subject: Re: [SI-LIST] Re:
Controlled ESR capacitor Hi Chris, Thank you for your comments.ÃÂ Both, 30-40
and 100-200 MHz jitterÃÂ components are important. There is noÃÂ point to
sacrifice one, or other.ÃÂ This was special experiment to validateÃÂ ÃÂ
the role of board decoupling onÃÂ interaction of two logic domains insideÃÂ
the chip which shared the sameÃÂ power supply: core logic was switchingÃÂ
(Aggressor) impacting routingÃÂ component's and clock tree' jitter
(victims).ÃÂ ÃÂ PLL on clock tree was using other, quietÃÂ power
supply.ÃÂ Scale is the same as onÃÂ figure 4: (jitter at core
switching)/(jitterÃÂ at core quiet). Let me know if you have more questions.
Thank you. Iliya On Aug 29, 2018 11:10 AM, "Cheng, Chris" wrote: Why do you
think it is worth sacrificing the 100-200MHz jitter performance with high cap
count for the narrow range of 30-40MHz jitter performance with lower cap count
? In the world of XbitY coding for the 10+Gb/s world, I would think the
100-200Mhz jitter performance is much more important than those 30-40MHz. To
me, the best conclusion I can draw from the two graph seems to point out the
price we pay for the obsession of jitter transfer over jitter accumulation.
Clearly the 30-40Mhz jitter peaking could be fixed by uping the PLL loop
bandwidth from around 10MHz to 40+MHz. In the name of saving a few $ in cheap
clock source, we paid this price for all PLL jitter accumulation downstream. To
recap : a) Who would feed a PLL with raw unfiltered power and rely on
decoupling cap ESR to maintain PLL jitter performance ? b) Why is it worth
sacrificing 100-200MHz jitter performance to a lower band 30-40MHz ? Also, what
was the vertical scale of the graphs ? Chris Cheng Distinguished Technologist ,
Electrical Hewlett-Packard Enterprise Company ÃÂ +1 510 344 4439/ Tel
chris.cheng@xxxxxxx / Email 940 N. McCarthy Blvd., Milpitas, CA 95035 USA
-----Original Message----- From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Iliya Zamek Sent: Monday, ;
August 27, 2018 8:39 PM To: binayaks@xxxxxxxxx Cc: dmarc-noreply@xxxxxxxxxxxxx;
Cheng, Chris ; tom@xxxxxxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx; FRED MOTTER ; FRED
B ; Jacques Tazartes ; EmadIbrahim ; Myrna5@xxxxxxxxxxxxxx; Istvan Novak ;
junichi.yamada.ak@xxxxxxxxxxx; Cosmin Iorga Subject: [SI-LIST] Re: Controlled
ESR capacitor Somehow my email was distorted. Re-sending.ÃÂ Hi Binayak, Your
effect description is correct. If you look at papers which links were included
in my email sent 2 days ago (August 25) you can see the graphÃâ that
described exactly the same - how low PCB impedance causes rising on-die
transients. If you could not find these papers, you might connect me off-line
and I'll send it to you. Thank you. Iliya.
------------------------------------------------------------------ To
unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in
the Subject field or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list For help: ;
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List forumÃÂ
is accessible at: ÃÂ ÃÂ ÃÂ ÃÂ ÃÂ ÃÂ ÃÂ
http://tech.groups.yahoo.com/group/si-list List archives are viewable at:ÃÂ ;
ÃÂ ÃÂ ÃÂ ÃÂ ÃÂ ÃÂ ÃÂ //www.freelists.org/archives/si-list Old ;
(prior to June 6, 2001) list archives are viewable at: ÃÂ ÃÂ ÃÂ ÃÂ ÃÂ ÃÂ
http://www.qsl.net/wb6tpu ÃÂ ------------------------------ Msg: #2 in ;
digest From: "Cheng, Chris" Subject: [SI-LIST] Re: Controlled ESR capacitor
Date: Fri, 31 Aug 2018 00:19:36 +0000 "it was demonstrated that the traditional
approach to the reducing PDN resonances by increasing the decoupling on PCB
does not help to remove resonance peaks." "Otherwise, lowering the PCB
impedance by adding more capacitances makes the situation even worse, - the
values of the peaks increase." The above statements are the reason why I feel
we cannot take this discussion offline and continue the discussion because
these are important concept I disagree with you. You are making the assumption
that jitter response to power noise is flat across frequency band and the
effect of decoupling strategy in power noise has a proportional impact across
all frequency band on jitter. It does not. The whole purpose of PLL is to
dynamically eliminate phase noise (jitter) either induced by power or clock
source. It can self-correct up to the PLL loop bandwidth which is set to
maintain stability also. The steep rise in jitter across all configuration
between 20-35MHz is not because your power noise is hitting a resonance, it is
because the PLL loop bandwidth is reached and the PLL starts to lose its
capability to correct the jitter. I would even venture to speculate the 35MHz
peaking is due to the PLL loop is slightly underdamped resulting in jitter
peaking. The point I am trying to say is both high cap and low cap count
configurations have resonance at low frequency, it seems the low cap count
happens around 10MHz while the high count around 35MHz. With the PLL loop
bandwidth being above one (low cap count) and below one (high cap count) there
are drastic differences between the two but you can't use that to conclude low
cap count noise is better than the high cap count based on the jitter
performance. In order to do that, you made the assumption power noise to jitter
transfer response is flat between 10 to 35MHz. It is not. This is like Gene
Simmons is playing in one room and Ozzy Osbourne is in another one. You put an
ear muff over my ear and walk me into Gene's room and then take it off and walk
me to Ozzy's room. Then you tell me, "See, Ozzy is noisy". Chris Cheng
Distinguished Technologist , Electrical Hewlett-Packard Enterprise Company ÃÂ
+1 510 344 4439/ Tel chris.cheng@xxxxxxx / Email 940 N. McCarthy Blvd.,
Milpitas, CA 95035 USA From: Iliya Zamek [mailto:i_zamek@xxxxxxxxx] Sent: ;
Wednesday, August 29, 2018 11:49 PM To: si-list@xxxxxxxxxxxxx; Cheng, Chris
Subject: Re: [SI-LIST] Re: Controlled ESR capacitor Hi Chris,ÃÂ Sorry for the
late reply; I was busy after work tonight.ÃÂ Thank you for reading my paper
"On-chip Jitter and system Power Integrity" DesignCon 2012. You are still
having in mind a design and how we can improve it, but this is not a case. This
paper main goals were:ÃÂ 1) to describe the method for PDN validation through
Jitter measurements which less impacted by parasitic and applicable for any ICs
weather they have special features, or not, that other methods require;ÃÂ 2)
using this method we revealed Jitter resonance induced by PDN noise that origin
of switching on-die logic.ÃÂ ÃÂ ÃÂ Note, that this is a characteristic of
PDN performance "looking from the die side". 3) next, using this method we
researched how on-board decoupling impacts the PDN resonances.ÃÂ ÃÂ The
method: two logic domains in standard FPGA were used that share the same PDN;
one logic domain was used as an Aggressor, and other as a Victim. Both were
switching periodically and asynchronously. Switching frequency sequentially
changing and Jitter of a Victim was each time measured.ÃÂ Jitter resonance:
switching of an aggressorÃÂ createsÃÂ pulses of a current corresponding each
rise and fall time of Aggressor signal; these current pulses causes PDN voltage
variations (noise). Changing Aggressor frequency we change noise frequency;
when noise frequency reaches PDN resonance the impact on the Victim became
higher and victim Jitter reaches the peak. So, this is a way to find a PDN
resonances.ÃÂ ÃÂ ÃÂ Decoupling: we changed on-board decoupling and
measured Jitter; we obtained that with rising decoupling at 36 MHz the
resonance became stronger and in field 100-200 MHz Jitter slightly reduced -
this effect also explained in paragraph following the graph. These measurements
are time consuming and we did not measure higher resonances. I think that
Jitter reduction at 100-200 MHz with increasing decoupling is an evidence that
higher frequency resonances also became more narrow and higher.ÃÂ ÃÂ ÃÂ
So, we did not sacrifice nothing; we just did an experiment, got data, and
explained the effects.ÃÂ I was glad to see Binayak' good explanation of the
effect that I also got from these experiments: looking from die capacitance
through package inductance to the decoupling we see parallel resonance. Its'
ESR is decreasing with rising number of the capacitances. When ESR is
decreased, Q-factor rising and, also, the resonance peak.ÃÂ ÃÂ ÃÂ
Chris,ÃÂ I agree with you that these results are important as an illustration
of new effects that has not been noted before: particular, it was demonstrated
that the traditional approach to the reducing PDN resonances by increasing the
decoupling on PCB does not help to remove resonance peaks. Otherwise, lowering
the PCB impedance by adding more capacitances makes the situation even worse, -
the values of the peaks increase. I will be glad to continue this discussion,
which is very interesting for me personally. However might be not all
Si-listers are interested in it;ÃÂ should we move it off-line? Best
regards,ÃÂ IliyaÃÂ ÃÂ On Wednesday, August 29, 2018, 4:59:50 PM PDT,
Cheng, Chris wrote: Your clarification makes me even more puzzled about your
conclusions. If this is general one die core noise to clock tree buffer power,
why would you sacrifice the critical >100MHz noise damping that most core logic
will care for the 30MHz or so that most switching logic don't care ? Is your
chip only working in 30-40MHz ? Back to the PLL jitter issue. As long as the
clock buffer output is used for the PLL phase detector input, it is still part
of the closed PLL controlled loop. You can see below 20MHz the PLL loop
bandwidth corrected the induced jitter on the clock tree buffer. You just luck
out that when the reduced cap configuration peaked around 10MHz, that was below
the PLL loop bandwidth. Had the PLL loop bandwidth is forced to be lowered by
crazy PLL spec like PCIE to 5MHz, the 10MHz peaking of the red curve will most
probably be higher than the high cap count configuration peak around 35MHz.ÃÂ
Sorry, these are important design trade-offs that I am not sure you have drawn
the right conclusion. We should keep this discussion going. Chris Cheng
Distinguished Technologist , Electrical Hewlett-Packard Enterprise Company ÃÂ
+1 510 344 4439/ TelÃÂ chris.cheng@xxxxxxxÃÂ / EmailÃÂ 940 N. McCarthy
Blvd., Milpitas, CA 95035 USA From: Iliya Zamek [mailto:i_zamek@xxxxxxxxx]ÃÂ ;
Sent: Wednesday, August 29, 2018 1:28 PM To: Cheng, Chris Cc:ÃÂ
dmarc-noreply@xxxxxxxxxxxxx;ÃÂ binayaks@xxxxxxxxxÃÂ ;ÃÂ
tom@xxxxxxxxxxxxxxxxx;ÃÂ si-list@xxxxxxxxxxxxxÃÂ ; FRED MOTTER ; FRED B ;
Jacques Tazartes ; EmadIbrahim ;ÃÂ Myrna5@xxxxxxxxxxxxxxÃÂ ; Istvan Novak
;ÃÂ junichi.yamada.ak@xxxxxxxxxxxÃÂ ; Cosmin Iorga Subject: Re: [SI-LIST] Re:
Controlled ESR capacitor Hi Chris, Thank you for your comments.ÃÂ Both, 30-40
and 100-200 MHz jitterÃÂ components are important. There is noÃÂ point to
sacrifice one, or other.ÃÂ This was special experiment to validateÃÂ ÃÂ
the role of board decoupling onÃÂ interaction of two logic domains insideÃÂ
the chip which shared the sameÃÂ power supply: core logic was switchingÃÂ
(Aggressor) impacting routingÃÂ component's and clock tree' jitter
(victims).ÃÂ ÃÂ PLL on clock tree was using other, quietÃÂ power
supply.ÃÂ Scale is the same as onÃÂ figure 4: (jitter at core
switching)/(jitterÃÂ at core quiet). Let me know if you have more questions.
Thank you. Iliya On Aug 29, 2018 11:10 AM, "Cheng, Chris" wrote: Why do you
think it is worth sacrificing the 100-200MHz jitter performance with high cap
count for the narrow range of 30-40MHz jitter performance with lower cap count
?ÃÂ In the world of XbitY coding for the 10+Gb/s world, I would think the
100-200Mhz jitter performance is much more important than those 30-40MHz.ÃÂ
To me, the best conclusion I can draw from the two graph seems to point out the
price we pay for the obsession of jitter transfer over jitter accumulation.
Clearly the 30-40Mhz jitter peaking could be fixed by uping the PLL loop
bandwidth from around 10MHz to 40+MHz. In the name of saving a few $ in cheap
clock source, we paid this price for all PLL jitter accumulation downstream.ÃÂ
To recap :ÃÂ a) Who would feed a PLL with raw unfiltered power and rely on
decoupling cap ESR to maintain PLL jitter performance ?ÃÂ b) Why is it worth
sacrificing 100-200MHz jitter performance to a lower band 30-40MHz ?ÃÂ Also,
what was the vertical scale of the graphs ?ÃÂ Chris ChengÃÂ Distinguished
Technologist , ElectricalÃÂ Hewlett-Packard Enterprise CompanyÃÂ ÃÂ ÃÂ
+1 510 344 4439/ TelÃÂ chris.cheng@xxxxxxxÃÂ / EmailÃÂ 940 N. McCarthy
Blvd., Milpitas, CA 95035ÃÂ USAÃÂ -----Original Message-----ÃÂ From:ÃÂ
si-list-bounce@xxxxxxxxxxxxxÃÂ [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf ;
Of Iliya ZamekÃÂ Sent: Monday, August 27, 2018 8:39 PMÃÂ To:ÃÂ
binayaks@xxxxxxxxxÃÂ Cc:ÃÂ dmarc-noreply@xxxxxxxxxxxxx; Cheng, Chris ;ÃÂ
tom@xxxxxxxxxxxxxxxxx;ÃÂ si-list@xxxxxxxxxxxxx; FRED MOTTER ; FRED B ; Jacques
Tazartes ; EmadIbrahim ;ÃÂ Myrna5@xxxxxxxxxxxxxx; Istvan Novak ;ÃÂ
junichi.yamada.ak@xxxxxxxxxxx; Cosmin Iorga ÃÂ Subject: [SI-LIST] Re:
Controlled ESR capacitorÃÂ Somehow my email was distorted. Re-sending.ÃÂ ÃÂ
Hi Binayak,ÃÂ Your effect description is correct.ÃÂ If you look at papers
which links were included in my email sent 2 days ago (August 25) you can see
the graphÃâ that described exactly the same - how low PCB impedance causes
rising on-die transients.ÃÂ If you could not find these papers, you might
connect me off-line and I'll send it to you.ÃÂ Thank you.ÃÂ Iliya.ÃÂ
intensive on-board decoupling does not reduce PDN resonances respect to the
chip die, but even make PDN performance worse, - resonances are rising.ÃÂ I
will be glad to continue this discussion, however might be not all Si-listers
are interested in it and we should move it off-line? Best regards,ÃÂ IliyaÃÂ
ÃÂ On Wednesday, August 29, 2018, 4:59:50 PM PDT, Cheng, Chris wrote: Your
clarification makes me even more puzzled about your conclusions. If this is
general one die core noise to clock tree buffer power, why would you sacrifice
the critical >100MHz noise damping that most core logic will care for the 30MHz
or so that most switching logic don't care ? Is your chip only working in
30-40MHz ? Back to the PLL jitter issue. As long as the clock buffer output is
used for the PLL phase detector input, it is still part of the closed PLL
controlled loop. You can see below 20MHz the PLL loop bandwidth corrected the
induced jitter on the clock tree buffer. You just luck out that when the
reduced cap configuration peaked around 10MHz, that was below the PLL loop
bandwidth. Had the PLL loop bandwidth is forced to be lowered by crazy PLL spec
like PCIE to 5MHz, the 10MHz peaking of the red curve will most probably be
higher than the high cap count configuration peak around 35MHz. Sorry, these
are important design trade-offs that I am not sure you have drawn the right
conclusion. We should keep this discussion going. Chris Cheng Distinguished
Technologist , Electrical Hewlett-Packard Enterprise Company ÃÂ +1 510 344
4439/ Tel chris.cheng@xxxxxxx / Email 940 N. McCarthy Blvd., Milpitas, CA 95035
USA From: Iliya Zamek [mailto:i_zamek@xxxxxxxxx] Sent: Wednesday, August 29, ;
2018 1:28 PM To: Cheng, Chris Cc: dmarc-noreply@xxxxxxxxxxxxx;
binayaks@xxxxxxxxx ; tom@xxxxxxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx ; FRED MOTTER
; FRED B ; Jacques Tazartes ; EmadIbrahim ; Myrna5@xxxxxxxxxxxxxx ; Istvan
Novak ; junichi.yamada.ak@xxxxxxxxxxx ; Cosmin Iorga Subject: Re: [SI-LIST] Re:
Controlled ESR capacitor Hi Chris, Thank you for your comments.ÃÂ Both, 30-40
and 100-200 MHz jitterÃÂ components are important. There is noÃÂ point to
sacrifice one, or other.ÃÂ This was special experiment to validateÃÂ ÃÂ
the role of board decoupling onÃÂ interaction of two logic domains insideÃÂ
the chip which shared the sameÃÂ power supply: core logic was switchingÃÂ
(Aggressor) impacting routingÃÂ component's and clock tree' jitter
(victims).ÃÂ ÃÂ PLL on clock tree was using other, quietÃÂ power
supply.ÃÂ Scale is the same as onÃÂ figure 4: (jitter at core
switching)/(jitterÃÂ at core quiet). Let me know if you have more questions.
Thank you. Iliya On Aug 29, 2018 11:10 AM, "Cheng, Chris" wrote: Why do you
think it is worth sacrificing the 100-200MHz jitter performance with high cap
count for the narrow range of 30-40MHz jitter performance with lower cap count
? In the world of XbitY coding for the 10+Gb/s world, I would think the
100-200Mhz jitter performance is much more important than those 30-40MHz. To
me, the best conclusion I can draw from the two graph seems to point out the
price we pay for the obsession of jitter transfer over jitter accumulation.
Clearly the 30-40Mhz jitter peaking could be fixed by uping the PLL loop
bandwidth from around 10MHz to 40+MHz. In the name of saving a few $ in cheap
clock source, we paid this price for all PLL jitter accumulation downstream. To
recap : a) Who would feed a PLL with raw unfiltered power and rely on
decoupling cap ESR to maintain PLL jitter performance ? b) Why is it worth
sacrificing 100-200MHz jitter performance to a lower band 30-40MHz ? Also, what
was the vertical scale of the graphs ? Chris Cheng Distinguished Technologist ,
Electrical Hewlett-Packard Enterprise Company ÃÂ +1 510 344 4439/ Tel
chris.cheng@xxxxxxx / Email 940 N. McCarthy Blvd., Milpitas, CA 95035 USA
-----Original Message----- From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Iliya Zamek Sent: Monday, ;
August 27, 2018 8:39 PM To: binayaks@xxxxxxxxx Cc: dmarc-noreply@xxxxxxxxxxxxx;
Cheng, Chris ; tom@xxxxxxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx; FRED MOTTER ; FRED
B ; Jacques Tazartes ; EmadIbrahim ; Myrna5@xxxxxxxxxxxxxx; Istvan Novak ;
junichi.yamada.ak@xxxxxxxxxxx; Cosmin Iorga Subject: [SI-LIST] Re: Controlled
ESR capacitor Somehow my email was distorted. Re-sending.ÃÂ Hi Binayak, Your
effect description is correct. If you look at papers which links were included
in my email sent 2 days ago (August 25) you can see the graphÃâ that
described exactly the same - how low PCB impedance causes rising on-die
transients. If you could not find these papers, you might connect me off-line
and I'll send it to you. Thank you. Iliya.
------------------------------------------------------------------ To
unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in
the Subject field or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list For help: ;
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List forumÃÂ
is accessible at: ÃÂ ÃÂ ÃÂ ÃÂ ÃÂ ÃÂ ÃÂ
http://tech.groups.yahoo.com/group/si-list List archives are viewable at:ÃÂ ;
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