[SI-LIST] Re: signal via to ground to ground via spacing more critical than most think
- From: "Istvan Nagy" <buenos@xxxxxxxxxxx>
- To: <doug@xxxxxxxxxx>, "Si-List" <si-list@xxxxxxxxxxxxx>
- Date: Mon, 24 Mar 2014 22:46:06 -0700
Hello Doug,
Do you analyze the via-via spacing on TDR plots?
Last time our contractor did that and seemed that we had too close vias and
ended up with 15 Ohm dips on the signal path's TDR plot.
After changing several layout design parameters including the signal via to
gnd via spacing and the via antipad size we reduced those dips on the TDR
plot to maybe 5 Ohms (I dont remember exactly). This was about matching the
via impedance with the line impedance.
The board was 18 layers, the signal was 10.3Gbit/s differential.
Basically I think we had to move the gnd stitching vias further away from
the signal via than it was originally. You suggested putting them closer.
Maybe you were talking about paralle busses changing layers while several
signals sharing one gnd via?
Then it is less about the impedance matching and more about (current and
return current) loop area reduction.
How do you quantify that? Or just do 3D-FW simulation with accurate/dense
GND plane mesh?
Regards,
Istvan Nagy
Fortinet
-----Original Message-----
From: Douglas Smith
Sent: Monday, March 24, 2014 9:26 PM
To: Si-List
Subject: [SI-LIST] signal via to ground to ground via spacing more critical
than most think
Hi All,
The spacing between a signal via and ground short via, or (on a four
layer board) a bypass cap, is much more critical than most believe and a
much smaller spacing is needed than one would expect from wavelength
effects. This data (added in the last week) and more in my one hour
webinar on treating an electronic system as a collection of (often
coupled) resonant circuits. URL for more information is:
http://emcesd.com/#Webinars . Next presentation is Thursday morning of
this week.
Doug
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========= Boulder City, NV 89006-0941
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| q-----( ) | o | Email: doug@xxxxxxxxxx
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