[SI-LIST] Re: signal layer between pwr/gnd layers
- From: steve weir <weirsp@xxxxxxxxxx>
- To: Tegan.Campbell@xxxxxxxxxxx, silist <si-list@xxxxxxxxxxxxx>
- Date: Tue, 18 May 2004 17:01:00 -0700
Tegan,
There are a couple of issues. The biggest is that by separating the power
/ ground pair, the inductance in that cavity will rise. That will do two
things, neither of which are good, but are not necessarily disastrous:
1) Increased inductance, sic higher impedance between the decoupling caps
and any powered IC.
2) Increased EMI due to less energy being required to excite the cavity by
the taller dimension, and more energy coupled to the cavity by the inserted
layer.
If you are not using a behemoth processor, or 40A ASIC the increase in
inductance is less likely to bite you on PDS requirements. But the
increased impedance and greater coupling of signal energy could cause some
real EMC headaches. Unfortunately, how bad depends on the specifics of
your system.
Regards,
Steve.
At 03:21 PM 5/18/2004 -0600, Tegan Campbell wrote:
>All,
>In trying to remove two layers from a 16 layer PCB I came up with a question
>I don't know how to answer short of building a board, which there is not
>time for.
>
>I have closed the loop on simulation/modeling vs measurement for a PDS with
>embedded capacitor using a 4 mil dielectric and capacitor array. I want to
>say thank you to Sun and Xilinx for the excellent work and papers they have
>published in the public domain on the subject.
>
>Now, I am having trouble working out what would happen if I insert a signal
>layer in between the planes. I need three signal layers to be referenced to
>a pwr/gnd pair, and that currently takes six layers(G-S-S-P-G-S). If I can
>insert a signal routing layer between pwr and gnd, it drops to five
>layers(S-P-S-G-S). This happens on two different pwr rails. My first
>reaction is the only difference would be the ~doubling of the distance
>between the planes. I can decrease this effect by using 3 mil cores.
>
>After thinking a while longer, it seems like there would be other
>differences from the copper in between the planes. It seems like I should
>be able to minimize the effect by using special spacing rules in the signal
>layer between the planes to maximize the ratio of dieletric area to copper.
>I think this would make the discontinuities in the dielctric(the copper
>traces) insignificant.
>
>I have not found a discussion of this specific PDS topic in the archives,
>and I apologize in advance if I am repeating something that has already been
>discussed.
>
>Any input or thoughts are appreciated, thank you for your time.
>
>Tegan Campbell
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