[SI-LIST] Re: signal Integrity starts at ?
- From: "Martin Mueller" <martinm@xxxxxxxxxxx>
- To: "Ravi chandra reddy" <vlsireddy@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Tue, 7 Dec 2010 18:20:07 -0800
Reddy,
SI issues can hit you at any frequency since it really is an edge rate
issue more than a frequency issue. Historically, you typically only saw
really fast edge rates with higher frequency devices which is where the
initial frequency based rule of thumb came into play. Obviously, at
lower frequencies you can also get away with a multitude of SI sins
since you have more time to allow things to settle down before you
capture the data (this, of course, ignores potential EMI problems, false
clocking, etc.).
---
Martin Mueller
Corsair
+1-510-657-8747 x267
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Ravi chandra reddy
Sent: Tuesday, December 07, 2010 5:58 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] signal Integrity starts at ?
Hi all,
I am new to this forum and this signal integrity area also. I am
into designing one adaptor board which connects between 2 SAMTEC
connectors.
samtec connector 1 <-----------> new adaptor board <---------> samtec
connector 2
both connectors are high speed connectors and since i am designing board
with mentor graphics PADS, how can i ensure that adaptor board is
SI-issue
free (using IBIS models, i can simulate and ensure that..but my question
is
mentor graphics PADS enoff to do SI analysis). somewhere i have read
that
signal integrity affects for signals > 40MHz only. adaptor board signals
operates at around 14 MHz to 20MHz. Will SI issue come into picture in
this
case.
can anyone please clarify regarding this.
thanks
reddy
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