[SI-LIST] Re: resend - Specctraquest model: mounted inductance
- From: "Bart Bouma" <bart.bouma@xxxxxxxxx>
- To: istvan.novak@xxxxxxxxxxxxxxxx
- Date: Mon, 16 Jun 2003 12:11:14 +0200
Istvan,
thanks for the detailed answer.
After the discussions during the past weeks on this subject (thanks also
go to Larry and Nick), I am aware that just a bare capacitor ESL value is
not of interest and useful for modern designs.
Question: what's the added value of having e.g. a Specctraquest model with
values for intrinsic and mounted inductance then?
That's where it all started about, maybe I'm wrong, but I believe that Sun
was involved in defining these models. Are these models superseded ?
Without knowing the configuration the inductance values listed in these
models are of no value for the end user. Please correct me when I'm wrong.
The tips you gave for the capacitor manufacturers at the bottom of your
answer will be helpful to give better defined "ESL"-values: we will study
these and see what's possible to realize.
Here some comments and remarks:
- a better internal construction: that is a lower profile, reversed
geometry capacitors like 0306 or even 0204 and e.g. X2Y-caps which exhibit
'inductance cancelation' by opposing currents ?
- geometry data of the capacitor, like cover thickness.
That would be no problem. It's -of course- known to us. I must study how
to publish this data, in datasheet?, on the website? or available on
request? .....
- Minimizing the cover thickness: we specify thickness of our products, a
series of capacitors in a given size have a specified thickness.
For capacitors with a low capacitance, the numbers of needed layers is not
sufficient to obtain the required thickness.
So we add, symmetrically at the bottom and the top side, cover layers
(just dielectric layers) until the required thickness is reached.
This is obviously not an advantage for having low inductance.
Better solutions:
no additional cover layers => thinner products (low profile). I will check
for possibilities in our process.
or
assymetrical cover layers (on top of the product only) => results in
products which have a prefered mounting orientation (this side up). Is
this desirable ?
Products have to be marked ...........!!!..........
Still we would face a minimum cover thickness of 80um (aprox. 3 mils),
which is needed to have reliable products.
- Construction detail and associated inductance in a set of representative
PCB connections (vs. numbers of vias, via diameter and distance etc).
Requires a lot of tests, etc.
I'm afraid that such only can be done for concrete (known) applications,
or eventually for some commonly used (general) configurations in order to
minimize the amount of variations.
Otherwise the amount of work would be so large that it should be done in
cooperation with other manufacturers and/or end users.
- Honestly I think that the situation having a set of "standardized" small
test boards with known geometry and containing the main connection options
is having more chances to be realized. Boards would be availble to vendors
and users (in fact we already did so with the small board having the 50
Ohm trace on it used for measurements in the Wiltron universal fixture).
I'm willing to promote this in our organization. I think it is beneficial
for both the customers and the manufacturers.
Istvan, since you are in this area and having the experience, could and
are you willing to provide us with a proposal for such a set of boards?
e.g. size, substrate material, thickness, copper thickness, pad layout,
via diameter and number of vias, interface(e.g. connectors) to e.g. VNA
for each case style/size?
Problem will be to get all manufacturers, vendors and users in the same
direction....
again thanks and best regards,
Bart Bouma
http://www.yageo.com
Bart,
Not copying the si-list on my previous reply that you copied to the
end of your message below was not on purpose, I was just in a hurry
and did not check the distribution list carefully.
I agree 100% with Nick that for the user the inductance number is
useful only if it reflects the same or very similar connection geometry
that he/she uses the capacitor in.
The current loop that determines the inductance goes through the
capacitor, and its external connections.
In the (today rare) case when the external path forms a big loop with
respect to the capacitor body, the partial self inductance of the
capacitor
body is a good and probably sufficient representation. This is the case
for instance when we use a capacitor to bridge a gap (say connect two
plane shapes) with no ground plane near by.
When we use surface mount capacitors connected to planes, the loop is
formed by the capacitor body, capacitor pads and vias and planes. If the
geometry is exactly known, the inductance can be determined at any
frequency. The inductance will be frequency dependent, partly because of
the change of current path inside the capacitor (as Larry described it in
the
ECTC paper), and partly because the change of current path in the pads
and vias. This frequency dependency (both inside and outside of the
capacitor)
gets small if and when the current loop is much bigger in size then the
thickness of the elements. For instance, if we use thin vias 100 or
200-mils
apart, connecting a low-profile capacitor from the top side of the PCB to
planes
on the bottom side of a thick board, the geometry does not allow for too
much
change of the current-loop size with frequency. In this case the coupling
between the capacitor's bottom and the closest plane may be weak, and
therefore breaking down the loop inductance or attached inductance to an
'inherent' inductance (say partial self inductance of the capacitor body)
plus
some external inductance may be accurate enough and may be easy to
estimate.
Surface mount capacitors with aggressive mounting, however, will pose
challenges. Consider the case, for instance, when the closest planes are
intentionally very close to the capacitor body. If the plane is say 3
mils nominally
below the PCB's surface, the distance between the capacitor's bottom
plates
and the PCB plane will have some uncertainty because of the highly
uncertain
thickness of PCB solder mask, copper plating, copper surface finish and
the
bottom cover thickness of the capacitor. The vertical distance of the PCB
plane
and lowest capacitor plate in practice could be anywhere between say 5
mils
and 20 mils, proportionally impacting the inductance. Similarly, when we
have
vias as close as 40 or 50 mils center to center, the via diameter plus the
drill
wandering (resulting in slightly different via locations) will have an
increasing
impact on inductance. The number of vias per capacitor, and in case
multiple
vias, the relative position and sequence of vias also changes the
inductance.
As a summary, the inductance depends both on the capacitor's internal
construction and its geometry of usage. And the more aggressive mounting
we choose, the more important the internal geometry details of the
capacitor
(and of the external connections) become.
Capacitor manufacturers could help the users in the following ways:
- by making sure that the internal construction of the capacitor helps the
user
to achieve low inductance with proper external connections
- by providing geometry data of the capacitor's internal construction
(e.g., by
specifying and minimizing the cover thickness)
- by giving the construction detail and associated inductance in a a set
of
representative PCB connections. If the options span a large number of
possible
geometries with sufficiently small granularity, most users should be able
to
estimate the inductance for a particular usage geometry by interpolation.
The
attached inductance could be given in a table, against the following input
parameters: number of vias (and via diameter), spacing of vias, distance
to
closest plane. This is still a multi dimensional space, so a careful
selection
and reduction of permutations is necessary.
Eventually I would love to see a set of 'standardized' small test boards,
with
published internal geometry, being available from capacitor manufacturers
so
that vendors and users could have the same exact structures to speak
about.
These small boards could represent some of the main connection options
for the given part. With standard surface-mount capacitor footprints,
these
boards should be the same for a given case style across all capacitor
values
and vendors.
Best regards,
Istvan Novak
SUN Microsystems
----- Original Message -----
From: Bart Bouma
To: istvan.novak@xxxxxxxxxxxxxxxx
Sent: Thursday, June 12, 2003 7:28 AM
Subject: Re: [SI-LIST] Re: resend - Specctraquest model: mounted
inductance
Istvan,
many thanks for your explanation. I really appreciate it.
w.r.t. ESL, I wrote an answer to Nick (cc. si-list). Please can you
comment on that too?
(I'm aware that this thread already did cost you and others precious
time).
It's discussing how to define ESL and how to measure it.
I pasted the content below:
thanks and best regards,
Bart Bouma
www.yageo.com
==================================================================
Nick,
thanks for response. It is very useful.
I'm not familiar with the terms self partial inductance etc.
But I think that we agree on folowing:
- such a wire has some kind of inductance (partial or self or else- )
- but it is quite meaningless.
More interesting, at least for me, ESL of capacitors.
It's good to know for us that an ESL value specified for MLCC's is quite
meaningless when it comes to simulation of circuits and multilayer boards
with planes.
But I think that it is still good as comparison to other components, it
gives at least an idea on possible improvements.
Condition: the measurements to extract ESL must be done in the same way
and with the same fixture, and this is certainly not the case.
you wrote:
" The ESL values published by capacitor manufacturers are not meaningful
or
helpful unless the test fixture and test method are well defined.
If you want to determine the ESL of a capacitor for a particular
application (e.g.
decoupling), it is important to measure the ESL in a fixture where the
capacitor is mounted in a manner that emulates your application. Any
attempt
to extract an 'intrinsic' inductance, attributable to the capacitor
only,
will result in a number that is of little use to anybody. "
But for a capacitor manufacturer it is impossible to give inductance
values for every application situation, in MHO the inductance will still
consist of two parts: the inductance of the part it self (call it
'intrinsic' and this should be supplied by the manufacturer) and an
inductance-value associated with mounting which must be extracted by the
simulation program used.
Measuring the inductance of a capacitor that is mounted in a de-embedded
and well defined fixture, like the ICM-fixture we have, would be
meaningful I think.
Or is the measurement described in the document comparing MLCC's with
X2Y (small FR_4 test board with microstrip line) a better way. More or
less simulating the practice (see link below)?
http://www.x2y.com/cube/x2y.nsf/(files)/X2YMLCC.pdf/$FILE/X2YMLCC.pdf
Nick, I like to have your comments on this, maybe (?) it will lead to a
standardized method of measuring inductance (or ESL) of decoupling
capacitors which can be used as a basis for simulations? Somewhere in the
simulation process you must assign a inductance property to the capacitor.
I don't know wether this is the right way, but maybe the measurements
described above can be a start.
As mentioned above, the loop-inductance then must be extracted by e.g. a
3D-solver from the given pcb-structure and geometry.
Makes this sense or is this too simple?
Any way, I'm willing to help in providing more usable ESL values for
e.g. multilayer ceramic capacitors, X2Y-capacitors and other types like
0306 (RG).
Bart Bouma
http://www.yageo.com
========================================================================================================================
Bart,
> Should I use this attached inductance as the "intrinsic inductance" of
the
> Specctraquest model?
The attached inductance should be the full inductance associated with
the
part.
Nick is correct that the 'intrinsic' inductance, which appears to be the
partial self inductance assoiciated with the capacitor body, may not
help
the user too much, because the attached inductance can be any higher or
lower
value due to mutual inductance in the loop (flux cancellation).
> Q: I assumed that the loopinductance consisted of the total inductance
of
> the whole loop, including the capacitor.
> Is my assumption wrong then? Is the definition of loop inductance
equal to
> total inductance excluding the capacitor?
Your understanding is correct, loop inductance is the inductance of the
loop, which includes the capacitor as well.
> Q: then, how to specify ESL for ceramic capacitors, both standard
> 2-terminal and 3-terminal ones?
> My idea: ESL = equivalent series inductance and should reflect the
partial
> inductance of the device.
> From your answer I understand, but correct me when I'm wrong, that
when
> we measure the ESL of a capacitor we actually measure the "loop
inductance
> associated with the capacitor", thus including plane inductance.
> When measured in a de-embedded fixture, don't we measure the
capacitor's
> partial inductance then?
I think the problem is that the term ESL came along at a time when these
minor differences in definition made much less difference, mostly
because
the geometry was much coarser. I am not aware of a commonly agreed upon
definition of ESL, so it is up to interpretation. Partial self and
mutual
inductances, mounted inductance, loop inductance, attached inductance
on the other hand have definitions, so by following the definitions, we
can use them correctly.
Best regards,
Istvan Novak
SUN Microsystems
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List archives are viewable at:
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List archives are viewable at:
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
