[SI-LIST] Re: remove non-functional pads
- From: lin-wl_wang@xxxxxxxxxxx
- To: yu.yanfeng@xxxxxxxxxx
- Date: Fri, 2 Apr 2004 11:51:40 +0800
Hi Yanfeng,
=20
I agree with you that it's not necessary to do the removal for MHz =
signals, but it may be a different thing if one have to deal with =
1-2GHz signals(in my case), and with 10Ghz signal in the future. And =
the board could be quite thick, 120-170mil or more. I also agree that =
2D&3D modeling and measurement should be conducted to verify the design =
rules before we decide to follow them. Currently I don't have =
oppotunity to use HFSS, but I plan to do a comparison by TDR or VNA =
measurement.
=20
Do you have the HFSS result and is it possible to share?
=20
Thanks!
Wang Lin
Agilent Singapore
=20
-----Original Message-----
From: yu.yanfeng@xxxxxxxxxx [mailto:yu.yanfeng@xxxxxxxxxx]
Sent: Friday, April 02, 2004 10:23 AM
To: WANG,LIN-WL (A-Singapore,ex1)
Cc: si-list@xxxxxxxxxxxxx
Subject: ??: [SI-LIST] remove non-functional pads
Hi, Wang=20
In Powpcb, there is no option to remove unconnected pads during =
gerber-data generation. However, most of PCB fabs will remove these =
unconnected pad for inner layers for process yield. Also, I don't =
think remove those unconnected pad will enhance the integrity of signal =
which through out via without a detail 3D analysis.In most case, the =
via length is very short and neglectable, compared to 1/20 wave lambda. =
If you wann keep impedence continuity for Mega Hz Signal, Please do a =
detail 3D analysis using Ansoft's HFSS and you will find more than a =
simple removal of unconnected pads.=20
There are lot of truths lies about SI. In our company, I see many =
people often prefer to do silly things instead of do quantitive =
analysis. I think this maybe a common phenomena.=20
Yanfeng Yu
Sr. Engineer
Nanjing R/D center, ZTE Corp.
63 Gongqingtuan Road, Nanjing 210012
Phone: 86-25-52872410
Mobile :13505159475
Mail: yu.yanfeng@xxxxxxxxxx=20
lin-wl_wang@xxxxxxxxxxx=20
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2004-04-02 09:48=20
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=E4=B8=BB=E9=A2=98=EF=BC=9A [SI-LIST] remove =
non-functional pads
Hello,
I would like to know how to remove those non-functional pads in order =
to reduce via capacitance? Manually or automatically by layout =
software?
Currently I'm thinking of two methods.
1.In layout design, define via in the way that:
(1) on all inner layers, pads defined as diameter=3D0 or 12, drilling =
hole=3D12mil(for example)
(2) on an inner layer where trace is connected, pads defined as =
diameter=3D20mil, drilling hole=3D12mil
To what I understand, the unnecessary pads will be removed, and the =
pads used to route out the traces will remain. But there're many errors =
when generating the gerber due to this removal. Don't feel comfortable =
with the errors. We're now using PADS PowerPCB, do not know if the =
software has a function to remove these pads automatically. Hasn't got =
reply from vendor yet.
2. or manually remove the pads in gerber file, but there're quite a =
lot.=20
How do you think about the two method? Is there any better way to =
remove?
Thanks!
-Wang Lin
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