[SI-LIST] Re: regarding Tprop definition in PCI
- From: "Ingraham, Andrew" <a.ingraham@xxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Mon, 12 May 2003 12:39:36 -0400
Adeel Ahmad,
I would not expect that "Tprop" means the same thing in different contexts.
The definition provided in the PCI specification is fairly specific and is
unique to PCI (not that you wouldn't find something similar elsewhere).
Someone else's "Tprop" may or may not mean the same thing. I've seen
"Tprop" used to mean the delay through a gate, or the clock-to-out delay of
a flop.
> 1. Consider the case -
> TX -----------------------RX
> in such a case the trace length will have a max. ONE SIDE delay of
> 2ns(PCIX) since RX(receiver) is placed only at the other end. Am i right
> in this?
Yes.
> Now consider another case-
> TX -----------------------RX
> |
> RX
> in such a case the trace length can be a such that ROUND TRIP delay is
> about 2ns(PCIX) since one RX(receiver) is placed very close to the
> TX(Transmitter) end. Am i right in this?
Yes.
> According the the book definition,however, in both cases trace length
> must have a ROUND TRIP delay of 2ns irrespective of receiver placement.
> Has the book definition taken for granted that receivers are also placed
> close to transmitter?
In general, most PCI buses are not point-to-point; most have multiple
devices spread along the length of the bus. In those cases, you have to
wait at least until the signal reflects off the end(s) of the bus and
reaches the receivers a second time, if not more, before the signals are
valid and stable. It's not precisely a full round-trip delay because the
driver never simultaneously receives its own driven signal, as you noted.
> 2. What is the significance of specifying Tprop(min) for Conv PCI33 as
> 0ns while specifying Tprop(min)=0.3ns for PCIX ?
My guess is that the PCI-X spec is being a bit more realistic, since it is
almost impossible to have zero wire delay from a driver to another receiver,
and easy to add that much wire delay if you need it. By doing so, they were
able to relax Tval(min) or Th(min) by 0.3ns, which perhaps wasn't such a big
deal at only 33MHz PCI.
Regards,
Andy
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