[SI-LIST] quickpath Interconnect design resources
- From: Randy Dawson <rdawson16@xxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Fri, 16 Nov 2012 15:01:52 -0600
Hi SI-LIST,
I am looking for design guidelines for the Intel QPI bus (Xeon E5), something
about the equalization and de-skew capabilities available in the processor that
will help me define the si constraints.
Can one of you folks point me to some design documents or constraint sets that
have worked for you?
Or an example 4 processor and I/O hub design?
Thanks,
Randy Dawson
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