[SI-LIST] Re: question about the bypass cap
- From: steve weir <weirsi@xxxxxxxxxx>
- To: zhao.dave@xxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Sun, 20 Mar 2005 03:42:24 -0800
David, You are on the right track, thinking about keeping inductance
down. What will work well all depends on:
1) What impedance profile you are trying to achieve, and
2) What the stack-up is of the board you are trying to use, and
3) Where you can physically put the capacitors in relation to the pins.
The short answer to your question is yes, but with conditions. But I think
that may be too short and simple to really tell you what you want to know.
I suggest you do some reading. You can search for any of the fine papers
done by various authors once or currently still at Sun Microsystems: Larry
Smith, Istvan Novak, Ray Anderson, etc. There are a number of books that
deal with power delivery such as Dr. Johnson's famous: "High-Speed Digital
Design", and "High Speed Signal Propagation". And then there are always my
papers on power delivery available on the Teraspeed, and X2Y web
sites: www.teraspeed.com, and www.x2y.com.
Steve.
At 07:03 PM 3/20/2005 +0800, david wrote:
>hi sir, i try to connect the bypass capacitor to the power pins of
>chips directly to reduce the induction of the circuit.Is it right?
>Generally, the bypass caps are connected to the power planes by a pair
>of vias and so as the power pin ,but i want to make the bypass cap
>and the power pin share the same via to cancel another pair. Is it
>feasible?
>
>
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