[SI-LIST] Re: now Behavioral Modeling
- From: "lgreen" <lgreen22@xxxxxxxxxxxxxx>
- To: "'Pratt, Gary'" <gary_pratt@xxxxxxxxxxx>
- Date: Mon, 21 Mar 2005 08:44:29 -0800
Hi, Gary,
Thanks for the added info on *-AMS. Very helpful!
- Lynne
-----Original Message-----
From: Pratt, Gary [mailto:gary_pratt@xxxxxxxxxxx]
Sent: Sunday, March 20, 2005 5:50 PM
To: lgreen22@xxxxxxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] Re: now Behavioral Modeling
Hi Lynn,
Thanks for the terminology clarification. I've always had an intuitive
sense for the terms, but its good to see a clear academic definition.
One minor bit of additional information ...
Lgreen wrote:
Most "AMS" languages restrict a model to contain either
equations or blocks (including components), but not both.
While Verilog-AMS has some restrictions in this area, they are not
difficult to work around.
VHDL-AMS has no such restrictions and allows analog equations, digital
statements, and block instances to be mixed in any arbitrary fashion.
Furthermore, the language places no restrictions on the source of the
instantiated blocks. In the case of the tool with which I am most
familiar, blocks can originate from VHDL-AMS, Verilog-AMS, SPICE, C,
Verilog, or VHDL (but sorry, no COBOL).
Regards,
Gary
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