Patolfo,
You should also consider input and output impedances. Assuming CMOS technology
for the actual gates, the inputs look like capacitors to VSS, and the output
has some series resistance. The datasheet should tell you both of these values.
Regards,
Weston
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Patolfo Nery Velya
Sent: Tuesday, October 24, 2017 8:34 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] modelling a gate a simple OR-gate from datasheet
Hello guys, does anybody can recommend a bkm for modelling a gate, taking the
datasheet data, without using a transistor level simulation, more like macro
modelling, I found out using VCVS one can model delay and current throughput
but what else should be included in the macro model for low speed signals like
50Megs or low?
The idea is to insert the gate into a strip line, STA gives no problem, and I
am guessing the actual transmission line would not give too much trouble, still
need to verify it.
al cabo de la vida quisiera descansar
en un bosque de paz y sin preguntas
y desde la espesura escuchar en sosiego
el preludio de un réquiem privadÃsimo
Benedetti **Cansancio
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