[SI-LIST] Re: minimum and maximum tracelength
- From: "kranthi" <kranthi.paturi@xxxxxxxxxxxxxxxxxx>
- To: <ppsadhak@xxxxxxxxx>, <chand_374@xxxxxxxxx>
- Date: Wed, 6 Sep 2006 15:00:57 +0530
Hi,
These timing margins are also a part SI that, how ever be the signal
good at electrcial levels, but it should be sampled at the right time to
ensure that correct data is received on the receiver side.
kranthi
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Hiten Bhagat
Sent: Wednesday, September 06, 2006 1:19 PM
To: chand_374@xxxxxxxxx
Cc: scott@xxxxxxxxxxxxx; hifrekwency@xxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: minimum and maximum tracelength
Hello,
Static timing analysis just makes sure that you meet setup/hold timing.
Not the noise margin. Minimum trace length limits are imposed to meet
hold time. It has nothing to do with noise, jitter, SSO etc. Meeting
hold time does not ensure that you meet all of the above parameters.
Hiten
On 9/6/06, chand basha <chand_374@xxxxxxxxx> wrote:
>
> Scott
> i feel both are same ? ?
> you need to meet timing requirement meance indirectly you are taking
> care of SI right ?
>
> chand
>
>
> Scott McMorrow <scott@xxxxxxxxxxxxx> wrote:
> Vignesh
>
> Minimum limits on trace length are usually for the purpose of timing
> closure, and not SI.
>
> regards,
>
> Scott
>
> Scott McMorrow
> Teraspeed Consulting Group LLC
> 121 North River Drive
> Narragansett, RI 02882
> (401) 284-1827 Business
> (401) 284-1840 Fax
>
> http://www.teraspeed.com
>
> Teraspeed(r) is the registered service mark of
> Teraspeed Consulting Group LLC
>
>
>
> Vignesh Upadhyay wrote:
> > Hi All,
> >
> > Some of the chip manufacturers specify minimum and maximum
> > tracelengths
> for certain interfaces like DDR, GMII etc.,
> > Is this minimum tracelenght have any relationship with SI ?
> >
> > Thanks
> > Paul
> >
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