[SI-LIST] Re: measuring i/o power without disrupting signalquality
- From: "Dean Gonzales" <degonzal@xxxxxxxxxxxxxxx>
- To: kflint@xxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Tue, 30 Jul 2002 10:04:13 -0700
Hi Kim,
You asked a very good question. One way to find the dissipated power is by
measuring the CASE temperature of the part - preferably with a non-contact
thermal couple. If you are provided with the thermal characteristics of your
substrate, then you can use the Psi(j-t) parameter to solve for the
dissipated power of the device. Note: Psi(j-t) determines the correlation
between Ttop, Tjunction & Power.
After you have solved for Tj, then you can solve for Power by the following:
(Tjmax-Tambient)/Theta(j-a) = Power.
One benefit of this technique is you get to observe the average power
dissipation for a standard system configuration that is running worst-case
stress patterns... while only considering the power draw of the device under
test. One downfall to this method is that its difficult to de-embed power
consumed by I/O from that of the core logic. In some cases this may not be
too much of a drawback - for instance if your device is used for shuttling
data back and forth (and not a bunch of serious number crunching) then the
core power dissipation may be far less than that of the I/O. So then you can
do some math to figure out what percentage comes from the I/O versus the
core logic based on gate counts and I/O capacitance.
Anyhow, one more tool to toss in the shed if you find it useful.
Have a good day,
Dean Gonzales
ServerWorks
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]On
Behalf Of Kim Flint
Sent: Monday, July 29, 2002 3:34 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] measuring i/o power without disrupting signal quality
Hi-
I'm developing a bringup board for a large ASIC project. One of the
things I need this board to do is provide a way to measure power
consumed in the I/O while running in system. We would then use this
information to check analysis of thermal and power supply requirements.
I'm concerned about how I might do this measurement without degrading
the signal quality and otherwise causing problems for the main goal of
ASIC validation. How do other people approach this problem?
The ASIC is a 788 ball BGA with two 64 bit 166MHz DDR/sstl2 memory
interfaces, one 16 bit 166MHz ddr/sstl2 memory interface, one 32bit in /
32bit out 100MHz cmos source sync interface, and one 100MHz 64bit cmos
common clock cpu interface. In other words, a whole lot of i/o running
at reasonably high speed, with potentially sensitive timing. The core of
the ASIC is 1.8V, and fortunately all of the i/o is separate on 2.5V. It
is a .18u chip, so rise times are likely in the neighborhood of a few
hundred ps.
Measuring the 1.8V core power is pretty easy, since I can isolate that
as it's own island with it's own regulator, and run it through a sense
resistor.
With the I/O however, I am concerned about isolating the ASIC i/o 2.5V
power from the i/o power of the devices it is communicating with. I
don't care much about layer count here, so I can easily add enough
ground planes so that the signals are only adjacent to ground planes all
the way. Is that sufficient for handling return currents? I think
current on 2.5 still has to return somehow, so I wonder if I risk
coupling or SSO related problems as a result of forcing that current
through some roundabout path to where I can measure it. Or would
switching current that does travel around be of sufficiently low
frequency to not cause me any trouble?
The second doubt I have is whether I will be able to get an honest
measurement of I/O power at all. Measuring current of a locally isolated
2.5V supply would help me with my power supply spec, but does that tell
me everything about how much power is actually dissipated in my i/o, and
thereby affecting thermal solutions? Here is my understanding of it,
perhaps some of you could check whether I've got it right or not?=20
With a cmos i/o driving 50ohm transmission line and another cmos
receiver, there will be some current driven from 2.5V to ground directly
through the transistors as the i/o switches. Measuring current on 2.5V
and multiplying by 2.5 would accurately represent this component. If the
i/o is switching high, current also drives through the high-side
transistor from local 2.5V into the line, charging the line to a high
level. Since the voltage across this transistor is changing, multiplying
that current component by 2.5V wouldn't accurately represent that power
dissipation. When the i/o switches low, current drives from the line
through the low side transistor to ground. This wouldn't be represented
in the local 2.5V current measurement at all. Measuring 2.5V current
doesn't appear to capture the whole picture here.
With the sstl2 ddr i/o, we have a termination resistor to 1.25V at the
far end. In this case when the i/o drives the line high, there should be
some initial power dissipation in the I/O as the voltage goes high. But
once the voltage is high, there is still current through the transistor
but the actual power is dissipating in the resistor, minus some in the
transistor due to the saturation voltage across it. Measuring local 2.5V
supply current in this case would not easily tell me how much was
actually in my i/o. Similar to cmos, switching low drives current from
the line and the termination supply, but not through the local 2.5V
power supply so that power dissipation is not represented in a
measurement there.
hmm, so I seem to be convincing myself that measuring current on my 2.5V
supply is not going to give me a correct measurement of power
dissipation in my i/o. Do you agree? Is there some other way for this
power to be measured? I'm curious how others address this, or if you do
what I've done in the past and convince everybody that it is too
problematic to be worth the trouble?
any opinions or suggestions are very much appreciated, thanks!
kim
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