SIwave is an hybrid solver 2D FEM for the planes plus 2D MoM for the lines
... then it combines the things together ... this is a very limited summary
of what itâs doing... but itâs not a 3D MoM or a pure FEM... please reach
out to your local ANSYS AE to get more info
The output of this tool is S-param... other format are a math
representation of S-param... like the RLCG full wave spice model
Everything is in a loop format as I explained in my original email
If you go in the lab and use a VNA to measure your PDN, can you separate
power rail from its reference ground?
Cris
On Tue, May 19, 2020 at 7:46 AM TangH <wang1.1@xxxxxxx> wrote:
Hi,Cris, The tool using for extraction is SIwave.
As far as I know, SIwave solve plane type by MoM solver ,but I have no
idea which file format should I choose.(FWS sub-circuit, RLGC sub-circuit,
Sentinel-SSO Netlist, Touchone File)
TangH
At 2020-05-16 14:43:42, "Cristian Gozzi" <cristian.gozzi@xxxxxxxxx> wrote:
Which tool have you used for the extraction?
The main topic here is partial inductance vs loop inductance
When you extract the pdn and you use a full wave solver FEM based you will
get the loop inductance and loop resistance... means only ports for
positive terminal and the reference is a common ground
This doesnât mean your ground bounce is not taken into account, but simply
you cannot split power bounce from ground bound or dc drop in power rail
from dc drop in ground... everything is in a loop format...
If you want to have the 2 effects separated you have to use a different
extraction tool based on partial RL solver like most of the MoM tools do
In this case you will get a dedicated pin for the power rail and dedicated
pin for ground
Then you can look at power bounce and ground bounce separately because the
tool extracted the partial self inductance of power rail and the partial
self inductance of the Ground plus the mutual between the 2
Note: with this method do not connect each ground pins To common ground
otherwise you will short out the RL portions of your ground and you will
get an optimistic response
I hope this help
Cris
On Thu, May 14, 2020 at 10:14 AM TangH <wang1.1@xxxxxxx> wrote:
Hello everyone,
Recently i have a study about PI+SI co-simulation. I have extracted the
PDN and got the 3 ports S-parameter file. The port 1 for cpu power, port 2
for DDR power and port 3 for VRM. So in the schematic diagram (using ansys
designer) I connected port 1 and 2 to corresponding ibis-model's power pin.
When the simulation is done. I noticed that level '1' is much worse than
level '0'. In my schematic diagram design, each port is only one pin
visible and is is ref GND by default, and the ibis-model ref GND too.It
means all port's GND and ibis-model's GND is short, the current does'nt go
through the ground plane any more.
What should i do if i want to probe the ground's voltage in each port, and
see the impact of level '0'.
Thanks
Tangh
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List forum is accessible at:
http://tech.groups.yahoo.com/group/si-list
List archives are viewable at:
//www.freelists.org/archives/si-list
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List forum is accessible at:
http://tech.groups.yahoo.com/group/si-list
List archives are viewable at:
//www.freelists.org/archives/si-list
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
