[SI-LIST] clock tree at GHz range

From: "lynda_liu123" <lynda_liu123@xxxxxxxxx>
To: si-list@xxxxxxxxxxxxx
Date: Wed, 18 Jun 2003 23:02:48 -0000

Dear SI gurus,

Does any one has experience on generating a clock tree running at
GHz range (routing couple of mm)? 

Differential clock tree has better noise rejection performance, but
it is very power hungry, besides, its driving capability and duty 
cycle can not compare with its CMOS counterpart. While CMOS clock tree 
is noisy. What kind of clock tree should I use?

Can any one, from the Signal Integrity point of view, give some ideas 
or share some experience on how to design and layout a low jitter, 
duty cycle balanced (50/50) GHz clock tree? 

Thanks in advance,

Lynda

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[SI-LIST] clock tree at GHz range

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