[SI-LIST] Re: clock simulation
- From: steve weir <weirsi@xxxxxxxxxx>
- To: venki.pras@xxxxxxxxx
- Date: Tue, 31 Jul 2007 17:21:51 -0700
Pras, run stock signal integrity evaluations including cross talk just
like you would any other signal. The clock net is only special in
that: monotonicity through the AC switching thresholds is paramount,
and jitter is costly. Adjust your pass / fail criteria accordingly.
Steve.
Pras venki wrote:
> Guys,
> Now I know that the clock net is a very critical net in the package and from
> my package RLC extraction it is found that the inductance is pretty
> significant on the clock net. Also it runs over all kinds of traces in the
> package.
>
> So how do I go about and simulate *relevant effects on clock signal by the
> package*? This is something which hasn't been addressed before, so I m
> basically setting up the simulation from scratch. What all issues will I
> have to address? For example, do I need information about the clock
> buffer/driver used and all that?
>
> I would really appreciate if you guys can give me any insight on how I can
> start.
>
> Thanks a bunch,
> Pras
>
>
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