hai I have some basic doubt in the high speed board design. 1.What is victim net? 2.What is physical rule ,electrical rule and parallelism rule? 3.what is capacitive and inductive impedence,how it will affect the signal quality? 4.how to find out the transmission line impedence. 5.Under what condition the normal signal(low speed) will become an transmission signal line(high speed)? 6.When to use 16/32 bit buffer(or)driver for processor bus lines,what is the need for? 7.What is aggressor nets? 8.What is Flight time? Regards Gopalakrishnan.S Project Engineer Wipro Technologies Lakshmi buliding,Begumpet, Secunderabad-500003 Tel-91-40-27906008,Ext-4625 Fax-91-40-27907123 -- Attached file included as plaintext by Ecartis -- -- File: InterScan_Disclaimer.txt **************************Disclaimer************************************************** Information contained in this E-MAIL being proprietary to Wipro Limited is 'privileged' and 'confidential' and intended for use only by the individual or entity to which it is addressed. You are notified that any use, copying or dissemination of the information contained in the E-MAIL in any manner whatsoever is strictly prohibited. **************************************************************************************** ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu