[SI-LIST] about the built in resistance
- From: Zheng Edison <edisonzheng@xxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Thu, 15 Jan 2015 22:18:20 +0800
hi,all:
I have a problem recently,in my application,a lvpecl driver interfaces with
a cml receiver with built-in resistance(ac coupled).the differential signal
quality measured at the receiver pins is good,while the simulation result using
ibis model at the same position has a very serious overshoot.In the simulation
scheme,I tried to add external 50ohm resistance at each end,connecting to
gnd.This time,the simulation result agreed well with the measure one. in my
opinion,the cml model of the chip should include the built-in resistance, but
in my case,it seems not.Did anyone have the similar
problem?------------------------------------------------------------------
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