[SI-LIST] Re: Why we need to use "Series resistor" at Transmi tter?
- From: Mike Brown <bmgman@xxxxxxxxxx>
- To: Deepali.Gupta@xxxxxxxxx
- Date: Fri, 01 Nov 2002 10:56:22 -0600
The spec that you cite is a DC spec and has relatively little to do with
the ability of the circuit to drive a line. To make that determination
- absent SPICE or IBIS models - you need to plot the device IV curves
with 50 ohm load lines to ascertain what the device behavior is when the
Vout is approximately VDD/2. In fact, we do this load line plot in
SPICE as a routine part of our IO analysis, as well as simulating the
net transient response.
If the driver is strong enough to drive the line, it will intersect the
50 ohm load line from v,i = (0,0) at something greater than VDD/2
(driving high). It will also intersect the 50 ohm load line from
(VDD,0) at something less than VDD/2 (driving low). These conditions
insure that the driver is capable of launching at least a half-amplitude
swing into the line. The series R is chosen such that at Iout =
VDD/2*Zo the resistor will drop any overdrive. The nominal value of R is
((Voh at i=VDD/2Zo) - VDD/2)) / (VDD/2*Zo)
That description of the choice is overly simplified. It assumes that the
line switches from a quiescent state - which isn't always true in
high-speed applications. The selection of the R is always a compromize
between the low drive and high drive requirements, and the variation in
driver IV curve with process and temperature. If you have the models,
run sims at all the corner conditions to insure that you understand the
timing and signal integrity behavior.
The device power dissipation will increase by (Zo-R)/Zo * F * C * V^2,
where F is the frequency (full cycle, rising and falling edge) and C is
the capacitance of the line and load.
The use of an external buffer will add skew, chip power, board area and
routing issues, and failure rate. It will solve any issues with the
source signal's drive capability, and it will move some IO switching
noise off the source device.
You don't say whether the net is point-to-point or multi-drop. If
multi-drop you are going to have to consider the round trip time to the
end of the bus and back to the nearest load in your timing analysis.
This is true whether you use the buffer or not, if the line is series
terminated. The buffer may offer the opportunity to drive a
full-amplitude signal into the line (using far-end termination) if
timing is critical. You can trade buffer delay for round trip time.
With a 12" net it's about a tie if the near load is close to the driver.
Regards
Mike
Gupta, Deepali wrote:
>Being that we are discussing series termination..........I have been using a
>series resistor on a 50ohm controlled impedance transmission line. The
>transmission line is 12" long. The driver characeristics has a Voh=2.3V with
>Ioh= -.1ma.
>Due to the length of the transmission line I have debating over the fact to
>whether use a Buffer/driver on the transmission line. Apart from having to
>manage skew issues and layout issues with the buffer what are the
>disdvantages of using a buffer over a series resistor.
>Usually what is the approx length of tranmission line is managed by just
>using a series terminator.
>
>Regards,
>Deepali
>
>-----Original Message-----
>From: Robert Kezer [mailto:Robert.Kezer@xxxxxxxxxxxxx]
>Sent: Tuesday, October 29, 2002 9:59 AM
>To: 'Michael.Chan@xxxxxx'; leeritchey@xxxxxxxxxxxxx;
>sandord@xxxxxxxxxxxxx
>Cc: si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: Why we need to use "Series resistor" at Transmi
>tter?
>
>
>
>Depends on how much the waveform slews into the loads. If the slew
>rate is long enough and the interconnect short enough one would not
>have to terminate.
>
>However, it is always wise to series terminate, it does not cost much
>to do it and it will allow for migration to newer and faster parts
>that may have to happen do to obsolence.
>
>Bob
>
>-----Original Message-----
>From: Chan, Michael (Eng Hou) [mailto:Michael.Chan@xxxxxx]
>Sent: Tuesday, October 29, 2002 11:28 AM
>To: leeritchey@xxxxxxxxxxxxx; sandord@xxxxxxxxxxxxx
>Cc: si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: Why we need to use "Series resistor" at
>Transmitter?
>
>
>
>I don't believe that statement is true. I have PCI bus that has 18 =
>loadings on it and it is never terminated ( 33MHz ).
>
>-----Original Message-----
>From: Ritchey Lee [mailto:leeritchey@xxxxxxxxxxxxx]
>Sent: Tuesday, October 29, 2002 10:18 AM
>To: sandord@xxxxxxxxxxxxx
>Cc: si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: Why we need to use "Series resistor" at
>Transmitter?
>
>
>The PCI bus, whick all PCs contain, is series terminated. How many =
>million of
>those are there? Just have to be careful when you clock data off the =
>bus.
>
>Lee
>
>Sandor Daranyi wrote:
>
>
>
>>>Jim,
>>>=3D20
>>>In regard to your comment: "Series termination
>>>shoulkd NEVER be used wher the path is going to more
>>>than one input i.e bus configuration.". The ATA/IDE
>>>interface used in PCs is series terminated at the
>>>source and is bussed to two loads on data and
>>>strobe lines. The number of working systems in the
>>>field is in the millions (every PC that has 2
>>>drives). The value of the series termination is a
>>>great consideration (in ATA it is 22-50ohms).
>>>=3D20
>>>So series termination in busses can work. Though, I
>>>recommend a thorough understanding of the system
>>>before employing this technique.
>>>=3D20
>>>=3D20
>>>Charles Hill, consultant
>>>
>>>
>>I concur. In theory, I agree that it's not "nice", but I've seen =
>>
>>
>series te=3D
>
>
>>rminations (with no parallel termination at the far end) used =
>>
>>
>successfull=3D
>
>
>>y in designs where there were multiple inputs on a trace. "Never" =
>>
>>
>sounds=3D
>
>
>> neat but as with most good rules, there are exceptions.
>>
>>I also agree with the caveats. In the examples I remember, the system =
>>
>>
>was =3D
>
>
>>running at a low clock frequency and all the inputs (not more than 3 =
>>
>>
>in t=3D
>
>
>>hat case) were close to each other at the end of a long trace. It was =
>>
>>
>of=3D
>
>
>> a daisy-chain topology, i.e. there were no branches on the trace, to =
>>
>>
>min=3D
>
>
>>imize the impedance discontinuities and reflections. The inputs had =
>>
>>
>high=3D
>
>
>> impedance. Of course, one gotta think twice, even thrice, before =
>>
>>
>doing =3D
>
>
>>this on a clock signal.
>>
>>Sandor
>>
>>---
>>Sandor Daranyi
>>Snr Design Engineer
>>Aristocrat Technologies Australia
>>
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