Hello Joel,
as others have pointed out, you'd need to supply some more details about the
way you arrive at these numbers.
Especially:
- actual geometry (microstrip vs. stripline, trace width, layer stackup, vias,
etc.)
- are these raw numbers or did you de-embed the trace (i.e. remove effects of
the launch points - reflections due to discontinuities at vias, contact pads
etc. can greatly influence the measured loss)
- at 3 GHz copper losses (skin effect) still play a major role
To minimize end effects (launch point contribution) I would suggest you use
traces that are as long as possible to make trace loss dominant, and place test
traces with at least two or three different lengths (but identical launch
structures) onto each board. This will make the de-embedding less urgent,
although it still won't get you around the influence of skin effect losses.
To reliably separate skin effect loss and DC loss from dielectric loss, you'll
need to measure loss at least two different frequencies (ideally do a sweep
over a broad frequency range). Since the losses scale differently with
frequency f (skin loss approximately with sqrt(f) and dielectric loss
approximately proportional to f) you can then do a curve fit to the measured
data points.
I did an article about this separation a few years ago:
http://www.pdamusician.com/testtechniques/files/easing_the_modeling_of_lossy_lines.pdf
This will work well as long as trace loss dominates over launch effects.
Best regards,
Wolfgang
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Joel Brown
Sent: Tuesday, April 07, 2015 11:01 PM
To: SI-List
Subject: [SI-LIST] Why is my PCB loss so high?
We have had several boards made from Isola FR408HR.
My understanding is that at 3 GHz loss should be about 0.3 db / inch.
On one board I am measuring about 0.76 db / inch, on another 1.4 db / inch.
What can account for this?
Thanks
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