[SI-LIST] Why has ODT control signals in DDR2 ?

From: liuluping 41830 <liuluping@xxxxxxxxxx>
To: FreeLists Mailing List Manager <ecartis@xxxxxxxxxxxxx>, si-list@xxxxxxxxxxxxx, si-list@xxxxxxxxxxxxx
Date: Wed, 05 Nov 2008 13:50:09 +0800



  Dear all:

        The ODT feature is designed to improve signal integrity of the memory 
channel by allowing the DRAM controller to
independently turn on/off termination resistance for any or all DRAM 
devices,and we will have 4 independent pins in a 
 Quad-stacked/quad-die DDR2 memory.

       I just curious why assign so many pins (more pins more costs) on the ODT 
controling ?
       To turn off the ODT when reading and turn on at writing the memory which 
the EMRS register can't do ?(I don't think it's necessary).
       To save power? May be few percent of the total DDR2 power consumption. 

Thanks and regards,


           LIU Luping

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[SI-LIST] Why has ODT control signals in DDR2 ?

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