[SI-LIST] Re: Where could I find the Hspice model of varactor?
- From: Yiran Chen <cyr_1976@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Thu, 11 Mar 2004 21:19:58 -0800 (PST)
Steven,
Yes, it is what I am thinking. However, I don't understand why you think it is
working at depletion state. When we apply VDD on the gate, a n-channel will
appears below oxide. I think it is accumulation. Am I wrong somewhere? Or the
misunderstanding of "depletion" and "accumulation". If you think it is NMOS,
that may be the reason why you are thinking it is depletion status. Right?
Sorry for such stupid questions.
Also, is it popular design for on-die decoupling capacitor? I know we could use
inversion NMOS and PMOS to implement the Decap but NMOS has large leakage
current and PMOS has slow speed? Are they the reasons to accept the design that
uses a NMOS in nwell?
Many thanks.
"Steven M. Waldstein" <swldstn@xxxxxxxxxxxx> wrote:
Yiren,
Are you really refering to on-die decoupling that uses a
NMOS in an NWELL? I know this is what TSMC refers to as a
varactor.
This is actually a depletion MOSFET. I know TSMC
has device models for these in there released HSPICE files.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of steve weir
Sent: Thursday, March 11, 2004 8:55 PM
To: cyr_1976@xxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Where could I find the Hspice model of varactor?
Do you really want to use a varactor as a decoupling capacitor??? The
capacitance of a varactor is typically in the 2-470pF region. That is not
going to make much of a decoupling capacitor. I think On-semi has models.
Steve
At 01:21 AM 3/12/2004 +0000, Yiran Chen wrote:
>I need such kind of model to implement a decoupling capacitance in
>my design.
>
>Thanks.
>
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