[SI-LIST] Re: Via modeling & de-embedding
- From: "package_char" <emc_gibney@xxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Mon, 19 Jul 2004 10:39:47 -0000
Hi,
Just another paper which maybe of interest:
G. Antonini, "S-Parameters Characterisation of Through, Blind and
Buried via holes", IEEE Transactions on Mobile Computing, Vol. 2,
No.2 April-June 2003
This paper discusses a de-embedding technique partitioning the test
structures between the via and mircostrip traces which provide a run
in to the vias. This paper also provides dimensions and stack-up
information of the test structures evaluated, which maybe a good
starting point for some 3D simulations.
Regards,
Eoin
emcgibney@xxxxxx
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