[SI-LIST] Re: Tradeoffs of split power plane vs. multiple power layers....
- From: steve weir <weirsi@xxxxxxxxxx>
- To: jon@xxxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Thu, 06 Apr 2006 00:25:44 -0700
Jon, your question covers a broad range of possibilities. Here are
two general cases I think are worth considering:
1. Suppose that we would like maximum route flexibility, that we
would like to route signals against any plane layer and switch
reference layers without concern. Then, we would need to tightly
couple the various planes together across our signal spectrum. In
the real world we can't get perfect coupling from DC to daylight. So
first we have to determine whether this approach is feasible, and
second we need to figure out what we need do to make it work so that
it better suits our goals than the alternatives. There isn't a
global answer. It boils down to numbers for specific cases.
2. Next suppose that we want to keep digital noise out of an analog
domain. To do that well we need to understand what needs to be
coupled, how we are going to couple it, and then how to really
isolate the rest.
Steve
At 08:42 PM 4/5/2006, Jon Anderson wrote:
>Greetings.
>
>I am curious to get some insight/opinions on power distribution
>approaches and the benefits of various configurations from an SI
>standpoint. Specifically, I am wondering how a split power plane
>within a single board layer affects SI, and the best methods for
>mitigating integrity issues (for example the use of multiple ground
>planes, or don't do split power planes since it's an SI no-no).
>
>It may be best to present an example. It is not unusual to see
>separate power (or ground) planes for analog and digital sections of
>a board. This is obviously done to provide isolation and limit the
>effects one section has upon the other. I am considering the
>tradeoffs of using multiple supply voltages/planes within a single
>board layer (which may be necessary in the case of an ) versus having
>to do unique layers for each voltage. Such a configuration might be
>necessary in the case of an ASIC that has multiple supply voltages
>but a common ground reference. Also, is it best to use matched
>power/ground layers for each voltage, even if the grounds are
>commonly referenced? If you do a split plane, are you as concerned
>with separate ground planes for each voltage?
>
>I understand that there are non-SI benefits to limiting the number of
>board layers (cost is the obvious one), but I'm strictly looking at
>this from a signal/power integrity standpoint. I also understand
>that the answers are likely application dependent, so I'm just
>looking for generalized reasoning why a specific configuration may or
>may not work well. I fully realize this is a series of very open-
>ended questions.
>
>For sake of arguement (and to simplify the situation), let's say that
>you can route all signals on the top and bottom layer, so any
>internal board layers would only be power or ground planes. I
>realize that the question becomes more complicated if you are looking
>to have internal ground planes specifically for isolation of signal
>planes.
>
>Thanks in advance.
>
>
>
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