[SI-LIST] Re: Trace Capacitance
- From: steve weir <weirsi@xxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Mon, 14 Nov 2011 02:11:16 -0800
It is hard to outguess a manufacturer's specifications. You could get a
hold of a demo board and load it with discrete caps and see how the part
performs. In any evaluation, make sure you have well isolated the
analog and digital supplies from each other.
Design alternatives using buffers include running either an end
terminated, or a mid damped bus. Either will spare you source
termination resistors on the tight ADC board. A third alternative is to
skip the buffer and overdamp the Tx lines in order to isolate the
capacitance on incident edges. This will of course impact the digital
signal integrity. Other alternatives include synchronizing the digital
noise to your analog sampling.
Steve.
On 11/13/2011 7:49 PM, johny leon wrote:
> Gurus,
> I am designing a system with two Analog Boards and one Digital Board. Digital
> board is on the backplane and the two analog boards connect to it through
> Samtec SEAM + SEAF-RA connectors.
>
> Analog board is having data acquisition system(DAS) and the ADC is working at
> 100MHz. Its 12 Bit PARALLEL data, which is going through the SEAF-RA+ SEAM
> connector to Digital board's Spartan-6. Analog Board trace length is 1.5" and
> the digital board trace is having 6" length.
> Now comes my question: As per ADC data sheet (LTC2252), Output capacitance
> shouldn't increase 10pF to avoid digital interference to the sensitive analog
> circuitry. Some online tools shows that this trace length (6"+1.5" + Conn)
> will give more than 10pF with my board stackup. Now I'm forced to use
> Buffers(6pF Cin) at the output of the ADC on the Analog Board to avoid this.
> I have 8 ADCs(100MSPS) on the analog board in addition to 4 DACs(100MSPS) and
> don't have enough space to add the buffer and series resistors(source
> termination). ADCs output structure is very good with enough drive strength
> and in-built 43E series resistor. But the buffers with in-built series
> resistor which I found(74LVC162244A) are having less drive strength at 1.8V
> of -2/-4mA(ADC to FPGA interface voltage). Simulation (Allegro PCB SI) shows
> good results for both circuits (with buffer and without buffer).
> 1) Should I worry about the output capacitance of the traces along with conn
> capacitance and add buffer?
> 2) Digital board is having two connectors to connect two Analog Boards.
> Analog board are similar and connects to two Spartan-6 FPGAs. These board are
> close to FPGAs and DDR3 memories on the Digital Board. ADCs and DACs on the
> analog boards will come to close to the FPGAs and DDR3s once the two boards
> are mated. Should I provide some shield connection option(GND-SLOT footprint
> to solder shield) on the Analog board to avoid potential Digital
> interference?
>
> Thanks in advance!
> Johny.
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--
Steve Weir
IPBLOX, LLC
150 N. Center St. #211
Reno, NV 89501
www.ipblox.com
(775) 299-4236 Business
(866) 675-4630 Toll-free
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