[SI-LIST] Testpoints on high-speed signals
- From: "Gareth Baron" <Gareth.Baron@xxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Mon, 17 May 2004 11:09:40 -0700
Guys/Gals,
We have recently come across an issue where we are at a bit of a =
cross-roads
and I would like some advice please.
Currently we are working on relatively tightly constrained designs where
propagation speeds and edge rates are important. We also want to design
these products so that they can be mass-produced. Since mass production
testers use a bed-of-nails kind of test we have traditionally been =
adding
test vias on all of our signals (35 mil pad expsed on the solder side of =
the
PCB).
Here's the issue: Since we have tight constraints (area and speed) I am
reluctant to add test vias on these nets. Obviously this affects the
testability of products.
I would like to know what other people/companies do about this issue. =
Is the
cost just factored into the yeild loss or are there other exotic ways of
doing testability on these nets (JTAG is not an option for us BTW) ?
Thanks,
Gareth.
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