[SI-LIST] Stackup issue
- From: <sathish.rajagopal@xxxxxxxxx>
- To: <si-list-bounce@xxxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Wed, 31 May 2006 15:46:00 +0530
Hello Gurus,
We are working on an aveonics PCB where high voltage(AC 115V) and low
voltage(5V) signals are used. Due to EMI/EMC issues, there are few design
changes and also we are intented to increase the stackup.
We are using the following stackup:
L1---HV
L2---HV
L3---HV
L4---HV
L5---HV
L6---HV
L7----Cu shielding between HV & LV signals
L8----LV & power
L9----LV
L10---LV
We are worried whether the above stackup does the proper isolation between LV
and HV signals.
Your comments are welcome.
Regards,
Sathish
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