[SI-LIST] Re: Stack up for EMI reduction, plane resonance and u-s trip radiation etc etc

  • From: steve weir <weirsp@xxxxxxxxxx>
  • To: "Michael E. Vrbanac" <vrbanacm@xxxxxxxxxx>, si-list@xxxxxxxxxxxxx
  • Date: Wed, 11 Feb 2004 16:09:01 -0800

Michael, continuing with snips:
At 05:30 PM 2/11/2004 -0600, Michael E. Vrbanac wrote:
>Nima's email was the original that started the thread several days 
>ago...  I have the
>copy here in my mailbox and referred to it when I wrote the last email....
>Continuing the dialog...  launching from your comments... and I'll 
>truncate the rest of the
>last message...
>re:  "Considerable energy from what would be only a standing wave can and will
>find its way out under many conditions. Agreed that CM is a separate issue of
>plane potential versus the chassis."
>Without doubt...  The funny thing is after solving countless (meaning I 
>lost count!)
>emissions problems, only once could I ever verify that plane resonance was 
>the real
>issue.  I say that as a result of "board scanning examinations" and 
>"distributed plane
>potential measurements.  With these tests, in the one case only, was a 
>defined standing
>wave pattern observed.  The rest of the time those issues were always 
>resolved by
>very well defined design corrections that directly addressed the real 
>issue that was
>present.  I say that only to make the point that I don't do "kludge fixes" 
>except at
>gunpoint. <grin>  I hate EMI problems resurrecting themselves to haunt me 
>and my

It is certainly going to depend on what the board geometry is and what 
excitation is available to get it going.

>Personally, I've actually seen more trace resonances (and resonance 
>artifacts due to
>geometrical features of those traces) than plane resonances.  In relation 
>to this, there
>was some comment about fences and that contributed to plane resonances but 
>I doubt
>that would be a hard and fast rule

Please no hard and fast rules.  As I said, I prefer fences for ESD, but 
give them their due for capping the tuned cavity.

>  and might actually be something that could happen
>but is not guaranteed.  My point comes from the fact that if an RF current 
>null of a
>standing wave appears at an "conveniently placed RF short" (at the null) , 
>the standing wave
>will act as if "nothing were there", making the point about fences causing 
>or facilitating
>plane resonances less than certain.

I think that we differ here.  I find the logic circular, so maybe you care 
to expand.  The standing wave is a result of the reflection.  So,  there is 
no way that I see to add or remove a short.  It was intrinsic.  Surely if I 
put a pin through coax, I am going to heat the heck out of the drive 
amplifier.  I don't see why you believe that a rectangular cavity is 
fundamentally different.

>Given that, it is granted that the more consistent
>a particular electrical feature appears on a plane the more likely a 
>stronger reaction to
>producing something quite significant (resonance-wise) will occur.

Agreed, so don't regularly space fence via patterns.

>re: "Ah yes, those devilish little details again.  As in frequencies 
>present in
>the package now go way beyond what we can convey through the package
>interconnect to the PWB.  At frequencies substantially above 100MHz I know
>of no way to tightly couple any IC to the plane beneath.  The best I know
>how to do is shield the overall structure.  If you have a secret for
>overcoming package impedance at 100's of MHz, and beyond, I am all ears.
>Hmmm... well, I agree with the 100MHz when all we are talking about is 
>"pins and balls"
>for package electrical connections.  I do not agree that is the end of the 
>matter.  I've
>designed with RF power devices and if we understand how we can get 
>significant power out
>of those devices without melting the leads off from the RF current density 
>issues caused
>by the skin effect, we can certainly understand how to get a lower powered 
>connected to the reference plane better.  My point is to say is that we 
>have the technology
>already... we just aren't using it to our advantage. When we finally do, I 
>predict that many
>of these issues will simply "go away".  Our problem is that we are fixated 
>on "pins and
>balls" for package connection methodology.  Its like we want to use 
>something comparable
>to "wirewrap" technology for sub-100nS signal transmission. When aspect 
>ratio of a suitable
>conductor is used, the inductance will drop and we'll all look back on it 
>and say "gee, why
>didn't we think of this sooner?"

I hope you do well with the patent.  In the meantime I take it that you 
agree that the planes don't provide a lot of CM reduction for HF currents 
in the ICs.

>re: "I have always seen this as a matter of reducing inductance for the first
>choice.  If we hold L constant and increase C by altering Er, then the SRF
>falls by 1/sqrt(Er_new/Er_old), and for a fixed resistance, Q also falls by
>a similar amount.  It is actually a little worse than this, as the reduced
>SRF drops R due to skin effect.  However, for the same constant R Q falls
>directly with reduction in L."
>But all you are doing is dropping the resonant frequency by increasing 
>C... not surprising.
>Dropping L under those conditions does drop Q and that's good but I think 
>there is more to it.
>Perhaps we can look at this another way by looking at all the 
>variables.  Actually, you
>need to handle the R first since that sets the baseline for overall 
>impedance, the reactive
>portion is frequency dependent, R is not... (R + jwL or R - jwC).  This 
>means that skin effect and
>surface area of the conductor must be accounted for in the problem.  To 
>set the "baseline" lower,
>the R must drop.  But a problem exists... dropping R always raises Q 
>since:  Q = X / R. Hi-Q creates
>a more efficient (less losses) resonance.  How do we solve this?  We make 
>the "drive point impedance"
>too low for the driver to drive at the unwanted frequency.  Why?  The 
>impedance mismatch not
>only causes inefficient power transfer to the resonant structure, it also 
>loads the "driver" down
>too far to be able to drive it effectively.  So what do we do?  Since Z = 
>sqrt (L/C), decreasing L
>drops the impedance as well as increasing C.  Since we have already known 
>that we can easily
>increase C (to a point) through closely spaced power planes, we can use 
>this method to decrease
>the power plane "transmission line" impedance.  We also know that we can 
>add to this method
>by locally loading the planes with selected capacitance but at higher 
>frequencies this becomes
>more difficult (but not impossible) for a variety of reasons.By providing 
>these additions, RF current shunt
>paths are provided to "ground", this is equivalent to the old term 
>"bypassing". (That term is sometimes
>used in place of  "decoupling" intending to mean the same thing but the 
>circuit functions are not the
>same.)  The only thing that's left is "L".  In reality, we (industry) 
>actually are leaving this term largely
>untouched as I was implying earlier.  When we explore what determines "L" 
>and how to reduce it, we
>have our generic answers on how to solve the problem.  So from my 
>viewpoint, we can say we treat
>"L" first but in reality we've left it for last.  (I do agree we probably 
>should have solved "L" first).

Michael that's a long paragraph, but in the end the RD version seems to be 
"reduce the plane height", to which we already agreed.

My point, and throw all the stones at it you like is that Q comes down 
directly with L, L is only coming down with height.  C increases as a side 
effect of that.

What I was challenging was the specific benefit to Q of raising Er, as that 
affects capacitance directly but only Z and Q at less than inverse square 
root.  It is less than square root, because lowering the SRF also reduces 
the skin resistance.

If I could get a really high Er, then I could damp out the parallel 
resonance with the discrete caps, but it takes a whole lot more C than a 
plane can practically give.  So inductance reduction, which means height 
reduction is the order of the day for Q reduction.  Istvan's solution is 
his DMB concept using either ARIES, or controlled ESR decoupling 
caps.  Each of those approaches has its own drawbacks.

>re: "Agreed, we can design well tuned or intentionally poorly tuned 
>antennae in microstrips.
>The point that had been circulating concerned the containment properties 
>of prepreg."
>Prepreg?  I was under the impression that pre-preg was (for FR-4 class 
>dielectrics) uncured
>epoxy glass dielectric substrate that was cured during the "press-up" 
>during fab.  Why would
>more recently cured FR-4 (cured pre-preg) act any different than pre-cured 
>FR-4 (core) if the
>basic materials are the same and the glass/epoxy ratio is the same?

The method that Lee has been advocating is a stack-up that buries the outer 
microstrip.  This is not about cured or uncured, it is about where the 
microstrip being below the surface of a material with an Er >> 1 as 
effective field containment, versus being a stripline.  I am sorry if there 
is any confusion about that.

>About that subject, it would seem to me that it would only largely affect 
>the launch angle off
>the microstrip trace due to it being more deeply embedded in a "non-air" 
>dielectric in addition
>to a reflection off the dielectric boundary back toward the inside of the 
>board due to the wave
>impedance mismatch. E and H fields penetrate a dielectric like that with 
>the E field lines being
>distorted but not necessarily altered a great deal.  Containment?  I don't 
>get it.

Follow the field lines West young man!!!  Due to the higher permittivity, 
the field concentration  close to the top of the trace is much greater than 
for a surface trace.  Consequently, it doesn't take a lot of the stuff to 
knock 15db or more off of the signal versus a surface microstrip.



>Best Regards,
>Michael E. Vrbanac

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