[SI-LIST] Re: Split Vdd for DDR
- From: steve weir <weirsp@xxxxxxxxxx>
- To: amahajan@xxxxxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Tue, 25 Nov 2003 09:28:28 -0800
Abhijit, the idea of such an approach is to track the local SSO
disturbances in the power at each receiving end. I believe the concept is
backwards. If anything, you want Vtt to track the signals from the source
ends, not be isolated from them, and even worse coupled to some other noise
source, ie the SSO at the receiving ends. I think the scheme you show is
an example of good intentions gone awry.
Steve.
At 05:03 PM 11/25/2003 +0530, Abhijit Mahajan wrote:
>Dear All
>
>There is a design that has a split Vdd (from AC point of view) between
>DRAM and the Controller. By this I mean the arrangement is as shown
>below:
>
>
>2.5Vfrom Regulator ---------------------Coil---------------DRAM_Vdd
> |
>
>+-----------Coil----------------Controller_Vdd
>
>
>I would like to know the pluses and minuses of such an approach. The
>conditions are given below:
>
>* Both Vdds are distributed with the planes.
>* Neither the planes nor the "plane-split" are anywhere near any of the
>signal traces.
>* Consequently none of the traces uses the Vdd planes for return
>current.
>* Vref is derived from the "DRAM_Vdd" with resistor divider and used by
>both the controller and DRAM.
>*The Ground plane is solid with none of the common problems.
>*The caps are well placed and tied nicely.
>
>The only problem I could think of is that this arrangement will need
>"ultra-clean" bypassing and may need double the bypassing of a normal
>Vdd/Gnd scheme.
>
>Any thoughts are welcome.
>
>Thanks!
>
>Abhijit.
>
>
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