[SI-LIST] Re: Source Synchronous timing analysis
- From: Cristian Filip <cris_filip2002@xxxxxxxx>
- To: si-list@xxxxxxxxxxxxx, pratap simha <pratapasimha@xxxxxxxxx>, SteveKaufer <steve_kaufer@xxxxxxxxxx>
- Date: Sat, 27 Feb 2010 09:16:24 -0800 (PST)
Hi Pratap,
As Steve mentions if you are looking at DDR technology it is better to upgrade
to HyperLynx 8.0 and use Mentor App Notes to create a timing model for your
memory controller. Then the tool will do the job for you, so you don’t have to
do manually timing budgets. You can check Micron’s web site as well for good
App Notes:
http://www.micron.com/products/dram/ddr/technotes.aspx
In case if you are not looking at DDR technology here is a document from TI
explaining in detail the recommended methodology:
http://focus.ti.com/lit/an/spra839a/spra839a.pdf
For pre-layout analysis you will have to build topologies in LineSim and get
the fligth time from simulation. If you have a routed board, you can run
Generic Batch Simulation from BoardSim and get the compensated fligth times.
Both HL7.7 and HL8.0 will work.
Hope this helps,
Cristian
--- On Wed, 2/24/10, Kaufer, Steve <steve_kaufer@xxxxxxxxxx> wrote:
> From: Kaufer, Steve <steve_kaufer@xxxxxxxxxx>
> Subject: [SI-LIST] Re: Source Synchronous timing analysis
> To: si-list@xxxxxxxxxxxxx, "pratap simha" <pratapasimha@xxxxxxxxx>
> Received: Wednesday, February 24, 2010, 10:55 PM
> Pratap,
>
> If you're thinking about DDRx interfaces, you're using the
> wrong version of HyperLynx. v8.0 has a feature which does
> all of the work for you: automated SI and timing analysis
> for DDRx, with setup in a step-by-step wizard. Contact me
> off-line if you need details.
>
> Regards,
>
> -Steve-
>
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Cristian Filip
> Sent: Wednesday, February 24, 2010 7:49 PM
> To: si-list@xxxxxxxxxxxxx;
> pratap simha
> Subject: [SI-LIST] Re: Source Synchronous timing analysis
>
> Hi Pratap,
>
> Check this out:
>
> http://download.intel.com/design/intarch/papers/321098.pdf
>
> Cristian
>
> --- On Wed, 2/24/10, pratap simha <pratapasimha@xxxxxxxxx>
> wrote:
>
> > From: pratap simha <pratapasimha@xxxxxxxxx>
> > Subject: [SI-LIST] Source Synchronous timing analysis
> > To: si-list@xxxxxxxxxxxxx
> > Received: Wednesday, February 24, 2010, 12:05 AM Dear
> All, For timing
> > analysis of Source Synchronous system, (using
> hyperlynx SI 7.7 and
> > excel spreadsheet for calculating setup and hold time
> margins ),
> > https://docs.google.com/fileview?id=0B-Z_ASQzzVXnOGVhODc0NDAtNDhmZi00N
> > GM1LTgyMzgtMzc0OGQwMWU0MTJm&hl=en
> >
> > how to obtain the value of T (dataClkTX) i.e delay
> between data and
> > clock at the transmitter, from datasheet or it should
> be obtained from
> > hyperlynx delay measurements.
> >
> > Thanks and regards,
> > pratap
> >
> >
> >
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