[SI-LIST] Some questions; high speed/high density
- From: "Manu Pillai" <mpillai@xxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Tue, 8 Jan 2002 14:06:05 -0800
Hi,
The recent thread on tented vias triggered some responses and some questions
from the back of my mind. Some explanations are in order:
1) Long ago, I used to work in an environment where there was a lot of
ICT/ATE - so tons of tenting and filled vias. I developed a strong dislike
for tenting after seeing boards damaged by unplanned shorts, etc. Hence my
bias. My apologies if you need to tent; if you do, you gotta do what you
gotta do.
2) More recently, I worked in an environment where ICT was considered
sacrilege; basically the Mfring guys considered it an insult to suggest they
needed ICT and delivered 99.97%+ yield, which we basically tested at system
power on. So tenting/ICT was a non- issue. I was pampered. I luxuriated in
this. Perhaps this won't happen again:-)
Now to my immediate questions:
Background:
We are working with some folks who are up to 44 layers of PCB. Vias are
still drilled, not laser cut. Aspect ratios are tight. Packages are mostly
BGA, 600~2500 pins.
Questions:
a) Are there solid rules to follow for parking test points on high speed
lines? (bus speeds > 200 MHz) What are the effects of populating a row of
signal/gnd test point pairs all in a row?
b) How reliable have blind/buried vias been found to be?
c) From SI perspectives, what are the merits/demerits of blind/buried vias?
Where can I find documented test results?
d) How are these issues currently tied in to signal chaining from
die<->pkg<->PCB? Any easy ways? Easy to use tools?
Thanks for your time,
Manu
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