[SI-LIST] Re: Signal and Power Integrity Panel Discussion Coming to Boston Area

  • From: Ambrish Varma <ambrishv@xxxxxxxxxxx>
  • To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
  • Date: Fri, 19 Aug 2016 02:59:43 +0000

Thanks for pointing it out Lyndell.

Here are the correct links:

What/When/Where:
      CDNLive Boston (register here:
https://www.cadence.com/cdnlive/ma/2016/pages/registration.aspx  ;)
      August 31, 2016
      Boston Marriott Burlington
      Burlington, MA

The CDNLive Boston conference agenda is here:
https://www.cadence.com/cdnlive/ma/2016/Pages/agenda.aspx


Thanks,
Ambrish.

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Lyndell Asbenson
Sent: Thursday, August 18, 2016 10:31 PM
To: Brad Griffin; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Signal and Power Integrity Panel Discussion Coming to 
Boston Area

All the links below give me an HTTP error 400 just fyi -Lyndell Lee Asbenson

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Brad Griffin
Sent: Thursday, August 18, 2016 4:54 PM
To: si-list@xxxxxxxxxxxxx
Cc: Brad Griffin <bgriffin@xxxxxxxxxxx>
Subject: [SI-LIST] Signal and Power Integrity Panel Discussion Coming to Boston 
Area

Greetings SI-List Friends,
I wanted to make sure all of our colleagues on the SI-list are aware of the 
upcoming event in Burlington, MA where some of our SI-list contributors will 
talk about some of the SI/PI challenges that are on the horizon.

The panelists include:
-       Istvan Novak - Senior Principal Engineer at Oracle
-       Kevin Roselle - Senior Staff Engineer at Qualcomm
-       Stephen Scearce - Senior Manager of High Speed Design at Cisco
-       Dale Becker - Chief Electronics Packaging Engineer at IBM
-       Ken Willis - Product Engineering Director of High Speed Analysis
Products at Cadence

Their kickoff topics include:
-       DC-DC Converters - it's a love - hate relationship
-       AMI models for memory interfaces: Single-ended signals need
equalization, too
-       DDR4-3200 - even the most experienced engineers can trip on this max
speed interface
-       System serial link compliance when utilizing multiple suppliers
(chip, package, board, connector)

Time will be reserved for Q&A.  The panelists are looking forward to your 
questions.

If you live in the area or you will be traveling to New England, we hope you 
can take the time to join us at this event.

What/When/Where:
      CDNLive Boston (register here:
https://www.cadence.com/cdnlive/ma/2016/pages/registration.aspx<https://www.cadence.com/cdnlive/ma/2016/pages/registration.aspx%20>
 )
      August 31, 2016
      Boston Marriott Burlington
      Burlington, MA

The CDNLive Boston conference agenda is here:
https://www.cadence.com/cdnlive/ma/2016/Pages/agenda.aspx<https://www.cadence.com/cdnlive/ma/2016/Pages/agenda.aspx%20>

I have a limited number of "promo codes" for SI-list members, so please contact 
me directly if you would like to register for the conference free of charge.

 Best regards,

Brad Griffin   |  Cadence Design Systems  |   Product Management Director,
SI / PI Technology


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