[SI-LIST] Signal Interface within CML and LVDS?
- From: "Inmyung Song" <imsong@xxxxxxxxxxxxxx>
- To: "Signal Integrity Mail Group" <si-list@xxxxxxxxxxxxx>
- Date: Tue, 12 Nov 2002 11:38:00 +0900
Good morning folks.
My customer wants to interface the signal between CML and LVDS.
But he don't know which value must be used for bias.
For example, when LVDS input must swing over 100mV then the signal is O.K.
How about center level for example, 1V(+50mV : 1.05mV, -50mV : 0.95V) must be
center?
Is there any constraint of center level in differential signal?
I think that the only eye open voltage is important, but not center level. Is
it right?
Any comment will be very helpful to me for example CML input, output IBIS model
or
other application note.
Thank you very much.
Inmyung Song.
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