[SI-LIST] Signal Integrity Job opening at Xilinx (Updated)

From: Ray Anderson <ray.anderson@xxxxxxxxxx>
To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
Date: Tue, 10 Feb 2015 00:02:53 +0000
Posting edited to update education requirement.
-------------------------------------------------------------


Xilinx has a Signal Integrity Sr. Staff Engineer opening immediately in the 
Package Design Department at Xilinx' San Jose headquarters.

The candidate will be responsible for driving package design integration, 
verification and characterization in advanced FPGA systems, incorporating 
silicon/TSV, package stack-up/routing/PDN, discrete decoupling capacitors and 
system board interfaces. Job requirements include the ability to utilize 
techniques in EM (Electromagnetic) and Circuit model generation, simulation, 
and validation for correlating hardware measurements versus pre/post-layout 
simulation, effecting a signal integrity driven design flow for advanced FPGA 
product development. While working as a member of a cross functional team, the 
candidate must optimize system level performance in areas including Power 
integrity, High speed IO/SSO, and Multi-Gigabit Transceivers. Drive cost 
reduction through adoption of leading edge package technology while achieving 
performance driven objectives.

Job requirement:
7 to 10 years of package design experience in high speed/RF/DDR designs, 
circuit and package modeling, extractions and characterization.
BS in EE or CS required. MS/PhD is desired
Past experience in large ASIC and FPGA package (>1900 pins) is desired
Other skillsets include:

§  Thorough understanding of all aspect of package design and relationship 
between physical layout and electrical performance.

§  Hands-on package design experience in high-speed IOs including multi-gigabit 
SerDes transceivers and DDR memory IO interfaces.

§  S-parameter modeling methodology, power Integrity concepts and principles, 
simulation/debugging insights, physical scaling/dimension implications to EM 
behavior of silicon circuits, transmission paths/media, discrete/passive 
components, and integration of silicon/package/capacitors/ printed circuit 
board structures.

§  Clear understanding of power distribution network design and optimization 
techniques.

§  Hands-on experience with EM tools/platforms such as Ansoft HFSS, Sigrity 
PowerSI/Speed2000/XcitePI/XtractIM, HSPICE/ADS S-parameter based simulations, 
Matlab/Python.

§  Experience in set-up, calibration and operation of TDR, VNA, BERT, 
Eye/Jitter measurements.

§  Cost conscious design principles and experience.

§  Design automation experience and script programming are plus and desired

Interested candidates are welcomed to send their resume or questions to Hong 
Shi at hongs@xxxxxxxxxx<mailto:hongs@xxxxxxxxxx>




This email and any attachments are intended for the sole use of the named 
recipient(s) and contain(s) confidential information that may be proprietary, 
privileged or copyrighted under applicable law. If you are not the intended 
recipient, do not read, copy, or forward this email message or any attachments. 
Delete this email message and any attachments immediately.


------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list

For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field


List forum  is accessible at:
               http://tech.groups.yahoo.com/group/si-list

List archives are viewable at:     
                //www.freelists.org/archives/si-list
 
Old (prior to June 6, 2001) list archives are viewable at:
                http://www.qsl.net/wb6tpu
[SI-LIST] Signal Integrity Job opening at Xilinx (Updated)

Other related posts:
