[SI-LIST] Re: Signal Integrity Job at Cisco, Bangalore
- From: "Ward, Richard" <richard.ward@xxxxxx>
- To: "olaney@xxxxxxxx" <olaney@xxxxxxxx>, "amiagra2@xxxxxxxxx" <amiagra2@xxxxxxxxx>
- Date: Wed, 9 Sep 2009 22:12:41 -0500
Glassdoor.com has a number of engineering salary ranges for Bangalore (under
advanced search).
While there don't seem to be any Cisco hardware engineering positions (only
software), there are some
at other large US-based companies. As you need to sign-up, which is a pain,
I'll quote what I see:
the rough ranges seem to be INR300k to INR1.3M ($6k to $27k USD).
Regards,
Richard
(Don't take this as fact or representative. No connection/affiliation with this
website, blah blah blah.)
________________________________________
From: si-list-bounce@xxxxxxxxxxxxx [si-list-bounce@xxxxxxxxxxxxx] On Behalf Of
olaney@xxxxxxxx [olaney@xxxxxxxx]
Sent: Wednesday, September 09, 2009 7:41 PM
To: amiagra2@xxxxxxxxx
Cc: design97@xxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Signal Integrity Job at Cisco, Bangalore
There's a non-answer for you. How about a median salary for this type of
position?
On Wed, 9 Sep 2009 18:22:14 -0700 "Amit Agrawal (amiagra2)"
<amiagra2@xxxxxxxxx> writes:
> It is negotiable.
>
> -----Original Message-----
> From: Oscar Lang [mailto:design97@xxxxxxxxx]
> Sent: Wednesday, September 09, 2009 5:58 PM
> To: Amit Agrawal (amiagra2); si-list@xxxxxxxxxxxxx
> Subject: Re: [SI-LIST] Signal Integrity Job at Cisco, Bangalore
>
> Mind posting the pay scale for this position?
>
>
>
> ----- Original Message ----
> From: Amit Agrawal (amiagra2) <amiagra2@xxxxxxxxx>
> To: Amit Agrawal (amiagra2) <amiagra2@xxxxxxxxx>;
> si-list@xxxxxxxxxxxxx
> Sent: Tuesday, September 8, 2009 12:18:40 AM
> Subject: [SI-LIST] Signal Integrity Job at Cisco, Bangalore
>
> We are looking an experienced signal integrity engineer in
> Enterprise
> Switching Technology Group (ESTG), Cisco, Bangalore, India. The
> description is given below. If you are interested in applying for
> Bangalore office, please send your resume or contact me directly.
>
>
> Best Regards,
>
>
>
> Amit P. Agrawal, Ph.D.
>
> Senior Manager, Hardware Engineering
>
> Enterprise Switching Technology Group
>
> Cisco, San Jose, CA
>
> amiagra2@xxxxxxxxx
>
> (408) 424-2732 (Office)
>
> __________________________________________________________
>
>
>
> JOB DESCRIPTION FOR SIGNAL INTEGRITY ENGINEER
>
>
>
> An experienced signal integrity engineer is being sought for design
> and
> analysis of high speed interfaces and power distribution network.
> The
> successful candidate will be part of signal integrity technology
> team
> and participate in the definition of chip, package, printed circuit
> board (PCB), and system interconnects. Within a concurrent
> engineering
> environment, the individual will be part of a larger team with
> system
> architects, logic designers, ASIC engineers, and SI engineers in
> creation of next generation networking products.
>
> This group works on present and next-generation cost-sensitive yet
> high
> performance and high volume products.
>
> Your responsibilities will include but not limited to:
>
>
>
> - Working experience in high speed serial I/O applications, PLLs,
> CDR,
> transceiver/SERDES operations
> - Definition of signaling and package technology for high
> performance
> ASICs
> - Simulating and/or analyzing and/or generating power delivery
> network
> requirements
> - Understanding signal integrity and timing in order to budget and
> evaluate trade-offs between design parameters to determine a
> solution
>
> space that is high volume manufacturability
> - Generating the routing requirements and electrical margins for
> specific interfaces and verifying their correctness
> - Designing and conducting detailed testing and measurements to
> collect
> data for validation and correlation of design analysis
> - Making recommendations to modify lab equipment and/or processes to
> establish or improve process feasibility and/or capability and
>
> increase efficiency
>
>
>
>
>
> Typically requires MSEE/CS combined with 3-4+ years of related
> experience, or BSEE/CS combined with 4-7+ yrs related experience.
> Proficiency with spice (or equivalent) circuit simulation,
> field-solver
> and time/frequency domain analysis, familiarity with high speed
> serdes
> design, PLL design and LVDS, SST, CML and other high-performance I/O
> technologies, ASIC design experience with I/O selection and
> simulation/validation, solid background on transmission line theory
> are
> necessary. In depth understanding of electromagnetics is plus.
> Experience with available CAD/CAE tools such as HSPICE, SiSoft,
> HFSS,
> CST, Sigrity Speed 2000, PowerSI, Si-Wave, Paksi-E, Sentinel_PI,
> Spicelink, Apache Redhawk/CPM, Agilent ADS, and Cadence SI tools or
> related tools. Experience in correlating simulation results with
> lab
> measurements using oscilloscopes, TDRs, VNAs, and spectrum analyzers
> is
> a plus. Self motivation, teamwork and strong communication skills
> are
> essential.
>
>
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