[SI-LIST] Signal Integrity Engineer Opening

  • From: "Xu, Chao" <cxu@xxxxxxxxxxxxxx>
  • To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
  • Date: Wed, 17 Jun 2009 11:24:55 -0700

Hi, All

We have a Signal Integrity Engineer opening position. Detail is below.

Please let me know if you are interested.

Thanks
Chao

----------------------------------------------------------------------------------------------
Inphi is seeking a Signal Integrity engineer for its fast growing line of 
products for telecom,
datacom, computing and test and measurement applications. The successful 
candidate will join
the high potential pre-IPO company, work at Inphi headquarters in Westlake 
Village, CA, USA.

Responsibilities

The Signal Integrity engineer will be responsible for system level signal 
integrity modeling,
characterization and simulations including PCB, package and silicon ICs. The 
engineer will
contribute to specification development of different products and 
subcomponents. The engineer
will provide guideline for package designers, PCB board layout engineers and IC 
designers.
May work with external vendors and contractors. The engineer will also have to 
understand
power integrity. Job functions include bench measurements, silicon circuit 
modeling,
channel characterizations and simulations, simulation scripts and automations 
development.

Requirements

*       Master degree in Electrical Engineering or BE with2+ years of related 
industry experience in signal integrity area.
*       Strong fundamentals of transmission lines, EM and microwave theory
*       Understand the basics of integrated circuits designs
*       Experience with VNA and TDR measurements for channel characterizations
*       Experience in using 2-D and 3-D EM tools such as HFSS, IE3D, ADS.
*       Experience in using circuit simulations tools such as Hspice, Spectre.
*       Board level layout experience (APD, PADS) is a plus

Skills

*       Understand high speed signal integrity and PCB and package power 
integrity
*       Understand high speed cell designs in ASICs including SERDES, PLL and IO
*       Good system level debugging / troubleshooting
*       Effective communication and presentation
*       Team player





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