[SI-LIST] Re: Series termination: common mode
- From: steve weir <weirsp@xxxxxxxxxx>
- To: Vinayak AGRAWAL <vinayak.agrawal@xxxxxx>, vinu@xxxxxxxxx
- Date: Thu, 30 Dec 2004 04:42:17 -0800
Vinayak, well actually that is a very good question. But it also
points-out that your project team probably needs to bring in a packaging
expert if you intend to succeed.
First, let us follow Dr. Archambeault's advice and leave ground to potatoes
and carrots. What we want to do is maintain a 50 ohm CPW, or CPWG
waveguide from the I/O pad to the PCB. So, even though there will be very
substantial inductance, distributed capacitance along the line will
maintain the impedance. To the extent that the two halves of the diff.
pair couple, the even mode impedance needs to be raised a little bit to
maintain the differential impedance at 100 ohms. Now when this thing
switches, three things will occur:
1) There will be a local redistribution of charge between the driver going
high and the driver going low. The shoot through, and local common mode
imbalance will determine the amount of charge that gets injected into the
local ground network beyond the pair. That is the current that will
contribute to SSO between the die and that long, long path back to the PCB.
2) As with 1) the high side supply will see some amount of noise current
injection due to the imperfections.
3) Two wave fronts will propagate down the two waveguides you need to
implement on their way to the package / PCB boundary. If you reference
them to the same rail ( logic common at the I/O cell usually being a good
choice ) both from the I/O cell all the way through the package and on the
application PCB, then you will minimize the cavity excitation, and most
energy will propagate towards your receiver, limited primarily by the
material losses.
Steve.
At 05:54 PM 12/30/2004 +0530, Vinayak AGRAWAL wrote:
>I still have one question (please don't be annoyed).
>
>In all these structures, even with on-chip bypass capacitors,
>I suspect the common-mode will still not be properly terminated
>
>For example in the Figure 29 (of SATA 1.0a specs) though
>structure 1 will easily provide 100ohm differential
>termination, both the pins are proper 50ohm only if the ground
>connection has very small inductance, which is very difficult.
>And I don't think bypass capacitor can help in this. So how is
>this sort of thing managed?
>
>Vinayak
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