[SI-LIST] Re: SSTL-2 ClassII termination.
- From: "D. C. Sessions" <si-list@xxxxxxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Sat, 4 Aug 2001 05:49:52 -0700
On Saturday 04 August 2001 04:36, rajat.chauhan@xxxxxx wrote:
> Hello all,
> JEDEC8-9A specifies AC test enviorment for SSTL_2 ClassII driver,
> shown below. This means that the driver design will be optimized for this
> enviorment (though may used in other enviorments).
We're really careful to not say, "test load" in JC-16.
Anyone who does, buys beer for the committee. The
preferred term is, "characterization load." That's because
we really don't care HOW manufacturers test their devices,
so long as they can ensure that the test method correlates
to proper device behavior.
[Snip ASCII art of driver, stub resistor, and double-terminated 50-ohm line]
> But I have seen in some of it's application (DDR SDRAM signaling) it is
> used with the scheme shown below.
[Snip ASCII art of driver, stub resistor, and single-terminated 25-ohm line]
> My question is:
> 1. What is the difference between the two and when one is preferred over
> the other?
From a driver design standpoint, the two cases are identical. Both of them
require a driver capable of inducing a (Vthac+noise) swing on 25 ohms
through a stub damper resistor. In general-case applications the line is
fairly symmetrical (the first case) and in DDR applications the line is quite
assymmetrical due to the nature of the DRAM/controller system.
> 2. Some pappers also says that series resistor Rs isolates the stubs from
> main memory bus. HOW?
The stub damper is handy in a couple of ways. For one, it limits the effect
of excessively strong drivers. Mainly, though, it limits the impact of line
stubs (mostly on the DRAM modules) on the incident wave.
In a main-memory situation, the controller typically drives directly into a
fairly
long "lead-in" line between it and the memory array, followed by a resistor,
the array, and finally the shunt terminator. This is a manufacturing necessity
and an SI nightmare.
The resistor between the lead-in and the array has the effect of making DRAM
reads operate more-or-less as reflected-wave events: the source is quite low
impedance due to the driver, nearby capacitance, and shunt terminator, so the
series resistor matches the higher-impedance lead-in line.
Writes are completely different. The controller is typically stronger and
faster
than the DRAM, so the launch wave into the lead-in is limited by the lead-in
impedance. The series resistor helps limit the ringing from that wave hitting
the much lower impedance of the DRAM array. The dampers on the
modules also damp the ringing from the stubs on those modules and allow
a greater and more consistent wave amplitude going down the array.
The shunt terminator is chosen as a compromise, since the smaller it is the
greater the current wave launched but the lower the final voltage swing.
Large terminator resistors result in slower edges at the array and lower
power, smaller ones give better read amplitudes and lower write amplitudes.
Hope that helps.
--
| The race is not always to the swift, nor the battle to the strong. |
| Because the slow, feeble old codgers like me cheat. |
+--------------- D. C. Sessions <dcs@xxxxxxxxxxxxxxxx> --------------+
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