[SI-LIST] Re: SSN analysis?
- From: "Mark Alexander" <mark.alexander@xxxxxxxxxx>
- To: <erdinih@xxxxxxxxx>, <james.f.peterson@xxxxxxxxxxxxx>
- Date: Thu, 3 Aug 2006 11:43:58 -0600
Ihsan,
I agree. If you take measurements at 5 different portal (spyhole)
locations, you'll get 5 distinct results. This kind of noise is highly
location-dependent. For the static-0 output, location is a dominating
factor (it's mostly crosstalk). For the static-1 output, location can
be secondary because the disturbance may be dominated by variation of
the IO power system voltage within the device. With static-1, you're
seeing a combination of IO power system disturbance as well as
crosstalk.
As for a "too much noise" metric, this is complicated. Looking for an
erroneous logic level is a good place to start, but often the thing that
causes a system to fail is timing variation of the IO interfaces (which
may occur long before a logic glitch). SSO noise can be thought of as
adding jitter to the various signals in the interface, reducing timing
margin.
-mark
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Ihsan Erdin
Sent: Thursday, August 03, 2006 10:03 AM
To: james.f.peterson@xxxxxxxxxxxxx
Cc: fasig.jonathan@xxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: SSN analysis?
One thing I can add to the 2nd method is about the selection of the
steady-state IOBs for the worst case SSN effect. That calls for
choosing the quite buffer(s) farthest from a ground/Vdd pin for low/high
steady-state analysis.
Regards
Ihsan
On 8/3/06, Peterson, James F (EHCOE) <james.f.peterson@xxxxxxxxxxxxx>
wrote:
>
> hello Jonathan -=3D20
>
> Do you want to estimate the amount of current rushing in or out of the
> Altera part, or do you want to analyze the impact of this current
surge?
>
> If it's the amount of I, then it is straight forward - but don't use
the
> old "hang a capacitor on the buffer" approach. Think transmission line
> and represent the t-line with a resistor equal to Zo and another
> resistor for Zs (source impedance) and then tie them to rails (note :
> there might be other resistors in the path depending on your HSTL term
> scheme). Solving for I (E/Rtotal) seems to line up very well with SI
> simulators that can measure the in-rush current (if you have one you
can
> just simulate to get the answer). then take this answer and multiply
> times the # of outputs switching at the same time for total surge
> current.
>
> If it's the second question (what does this current surge do to my
> Altera's internal PDS?), then I can't help as much (sorry). There is a
> technique that's sometimes called the "portal method", that is used to
> look inside the device. Attach a scope to a quiet buffer driving high.
> Switch all the outputs from a 0 to a 1 and note the noise spike on the
> scope (the buffer is driving 1 so you are looking at the Vdd rail).
Then
> have the quiet buffer drive a logic 0 (Vss rail) and switch all of the
> outputs from a logic 1 to 0 and note the noise spike. I've used this
> method on large devices and it seems to work ok, but it needs a fast
> scope.=3D20
>
> The missing part of this is when will the part fail. This is usually
> defined as when a quiet buffer toggles because of all the noise...I'd
> try to get Altera to help you with this.
>
> Hope this helps.
>
> Jim
> Honeywell
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Fasig, Jonathan L.
> Sent: Thursday, August 03, 2006 9:45 AM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] SSN analysis?
>
> We are working on SSN analysis for an application that will have 600
> HSTL I/O's on an Altera Stratix-II GX130. Is there anyone in this
> community who has done (or is currently doing) similar work?
>
> jf
>
> -------------------------------------------------------------------
>
> Jonathan Fasig Email: =
fasig.jonathan@xxxxxxxx=3D09
> Mayo Foundation
> 4001 41st Street NW=3D20
> MSC Sn 2-132 Phone: (507) 538-5464
> Rochester, MN 55901 Fax: (507) 284-9171
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