[SI-LIST] Re: [!! SPAM] Re: Re: 50 Ohm Via?
- From: Scott McMorrow <scott@xxxxxxxxxxxxx>
- To: Vinu Arumugham <vinu@xxxxxxxxx>
- Date: Fri, 11 Jan 2008 15:12:47 -0500
Good point Vinu! In reality, the signal has a slightly longer path
length as it spreads across via pads. That will add an additional 5
mils per pad path length for thin boards (10 mils total) which would
increase the total path length in an 100 mil board to 110 mils, about a
10% increase, depending on the pad size. You can look at this as
additional capacitance loading the circuit, or as a longer path length.
I like the longer path length explanation, since the Er of the material
(and therefore the signal propagation velocity) does not change, just
because there are via pads. However, either way you correct the model
and simulate it you'll get the same results, until other full-wave
effects start to come into play.
Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax
http://www.teraspeed.com
Teraspeed® is the registered service mark of
Teraspeed Consulting Group LLC
Vinu Arumugham wrote:
> The pad/anti-pad capacitance also seem to increase the effective
> propagation delay. I get better results using transmission line
> models with 190 ps/in for 1mm pitch BGA vias and 210 ps/in. for older
> backplane connector vias on FR4 boards.
>
> Thanks,
> Vinu
>
> Scott McMorrow wrote:
>> Joel
>> As along as the via is short w.r.t. the signal bandwidth, the excess
>> capacitance of the pads can be lumped into the transmission line
>> approximation. You could break apart a via, layer by layer, with
>> accurate PEEC RLC modeling, but it would not buy you anything for
>> modeling of most signals. It is only when you are concerned about
>> energy injected into the planes, via electrical lengths that approach
>> 1/5 of the signal bandwidth, or via stub lengths that approach about
>> 1/10 of the signal bandwidth, that more detailed modeling is generally
>> necessary.
>>
>> As a first approximation, compute your via and via stub delay, and then
>> simulate the via with 30 ohm single-ended transmission lines. If the
>> simulation works, you're probably good to go, as long as you don't have
>> some awful via coupling going on. Then do a frequency sweep on the
>> circuit to determine where the worst-case quarter wave resonance cutoff
>> is. Once you find the quarter wave resonant frequency, you'll find that
>> at about 1/2 of that frequency your circuit has about -3 to -6 dB of
>> extra loss. If you're operating within one to two octaves of the
>> quarter wave stub resonance, it's a good idea to do more detailed
>> modeling, redesign your vias, or drill them out.
>>
>> regards,
>>
>> Scott
>>
>> Scott McMorrow
>> Teraspeed Consulting Group LLC
>> 121 North River Drive
>> Narragansett, RI 02882
>> (401) 284-1827 Business
>> (401) 284-1840 Fax
>>
>> http://www.teraspeed.com
>>
>> Teraspeed® is the registered service mark of
>> Teraspeed Consulting Group LLC
>>
>>
>>
>> Joel Brown wrote:
>>
>>> Scott,
>>>
>>>
>>>
>>> I like that approach because it is simple and easy to understand and
>>> simulate.
>>>
>>> The question I have is does it take into account the capacitance of
>>> the via?
>>>
>>> I know that greater capacitance translates to lower impedance, so does
>>> varying the impedance in effect include the effects of the via
>>> capacitance or does it have to be considered as a separate lumped
>>> element from the via transmission line model?
>>>
>>>
>>>
>>> Thanks -- Joel
>>>
>>>
>>>
>>>
>>>
>>> ------------------------------------------------------------------------
>>>
>>> *From:* Scott McMorrow [mailto:scott@xxxxxxxxxxxxx]
>>> *Sent:* Thursday, January 10, 2008 8:07 PM
>>> *To:* wolfgang.maichen@xxxxxxxxxxxx
>>> *Cc:* Joel Brown; Aubrey_Sparkman@xxxxxxxx; luant@xxxxxxxxxxx;
>>> si-list@xxxxxxxxxxxxx; si-list-bounce@xxxxxxxxxxxxx
>>> *Subject:* [SI-LIST] Re: 50 Ohm Via?
>>>
>>>
>>>
>>> In general, I agree with Wolfgang.
>>>
>>> If you want a good approximation for the time domain behavior of a
>>> via, just do a simple transmission line simulation and substitute a
>>> short transmission line for the via and the via stub. For thin
>>> boards, like the 0.09" board mentioned, try your simulations with a
>>> 30,35,40,45 and 50 ohm. A via in an 0.090" FR4 board will have a
>>> total length of around 15-16 ps. (prop delay of a signal in FR4 with
>>> an Er = 4.0 is approximately 170ps/in). The trace to trace path
>>> through the via is modeled as an in-line transmission line, and the
>>> stub is modeled as an open stub transmission. Both will have the same
>>> impedance, with their delay computed by multiplying the section length
>>> in inchs by 170ps (for FR4).
>>>
>>> This type of model will correctly show the stub quarter wave
>>> resonances, any ringing due to impedance discontinuity, and half-wave
>>> resonances that occur between the via and other vias, connectors,
>>> trace mismatches ... etc. Although the model is approximate, it will
>>> give you a good feel for how vias affect signal transmission.
>>> Transient simulations will show ISI effects, whereas frequency sweeps
>>> will show the more critical frequency domain behavior.
>>>
>>> Some engineers get hung up on how a via may respond to a particular
>>> edge rate. However, signal edges are quickly filtered by package and
>>> trace losses. What I find generally more important is how the via
>>> structure attenuates a propagating signal at the minimum bandwidth
>>> needed to receive the signal on the far end. This will usually be at
>>> a frequency of 1/2 the bit rate. In that case, for PCI Express Gen 2,
>>> the frequency of interest is 2.5 GHz, which is far below the bandwidth
>>> required to support a 30 ps signal edge.
>>>
>>> If signaling period/2 >> via delay, then very little full wave signal
>>> leakage into the planes will occur, and there will be insignificant
>>> impact on the insertion loss of a single trace/via combination.
>>>
>>> Scott
>>>
>>>
>>>
>>> Scott McMorrow
>>> Teraspeed Consulting Group LLC
>>> 121 North River Drive
>>> Narragansett, RI 02882
>>> (401) 284-1827 Business
>>> (401) 284-1840 Fax
>>>
>>> http://www.teraspeed.com
>>>
>>> Teraspeed® is the registered service mark of
>>> Teraspeed Consulting Group LLC
>>>
>>>
>>>
>>> wolfgang.maichen@xxxxxxxxxxxx <mailto:wolfgang.maichen@xxxxxxxxxxxx>
>>> wrote:
>>>
>>> Joel,
>>> actually your numbers are borderline for being concerned. Keep in mind,
>>> the 6x rule is really just a rough rule of thumb. For example, I did a
>>> quick simulation for a signal with 40ps rise time (T10/90), your 7.5 ps
>>> via, assuming the via impedance is 25 Ohms (i.e. it is too capacitive).
>>> Looking at the simulated TDR shows a reflection of about 10%. Now is that
>>> something to be concerned? Depends on your situation.
>>>
>>> First, a 10% reflection can cause data dependent jitter of (again, rough
>>> rule of thumb) +/-(Tr x 10%/100) = +/-4 ps. That means your data eye
>>> opening will shrink by 8ps. That assumes the reflection bounces oof the
>>> driver and eventually makes it to the receiver. If that is an issue will
>>> depend on how large the timing margins in your design are.
>>>
>>> Second, you may have more than one via in your path. If you are really
>>> unlucky, then the reflections from both vias just coincide (e.g.
>>> relfection from previous edge coming back from one via, and reflection
>>> from two edges before from second via). If that happens or not will be
>>> highly sensitive to your data rate and to the location of those vias. In
>>> this worst case your eye degradation would now be 16ps.
>>>
>>> One the other hand, reflection may not matter too much if your driver is
>>> impedance matched to 50 Ohms (or 100 Ohms differential). That's the case
>>> for many CML drivers, but not for PECL driver (they are around 7 Ohms). In
>>> this case the driver will swallow the reflection.
>>>
>>> Similar simple estimates and simulations can be done for e.g. rise time
>>> degradation, or for the stub (e.g. approximate stub and surrounding planes
>>> as a cylindrical capacitor).
>>>
>>>
>>> The way I usually decide how much effort to put into simulation, I usually
>>> start out like this:
>>>
>>>
>>> (1) use rough rulse of thumb, order-of-magnitude-estimates, or experience
>>> from previous similar situations to get a feeling where I am. Three
>>> possible outcomes:
>>>
>>> - E.g. if the via has 7.5ps prop delay and I am using a signal from a
>>> Microcontroller with 5ns rise time, I can already tell I won't have a
>>> problem. Done. No need to spend a lot of time simulating this, the answer
>>> would stay the same.
>>>
>>> - On the other hand, if my rise time is 15ps I can already tell I will
>>> have a big issue. Done. No need to run a lot of simulations to find that
>>> out. Instead spend the effort on figuring out fundamental improvements to
>>> the design: maybe use controlled impedance vias (this may take some field
>>> solver work); maybe I can reduce the board thickness. Maybe I should try
>>> to avoid vias on this critical path, keep it a surface trace. And so on.
>>>
>>> - Finally, if it's borderline (like the case above), that's the situation
>>> where I feel a good model and a good simulator adds most value, because
>>> only this can tell me beforehand if I should change my design or if I am
>>> fine.
>>>
>>>
>>> (2) once I decided that I have to do more modeling and simulation, I still
>>> wouldn't go straight to the most powerful, complicated, expensive piece of
>>> software I can find. Oftentimes you can get very far with simple,
>>> easy-to-use tools to improve your understanding. Personally I particularly
>>> like the Student version of PSpice (because it can deal with differential
>>> transmission lines), the TNT field solver (from Sourceforge, for 2D
>>> simulations of impedance, crosstalk), and recently Gore's TLineSim (online
>>> tool, http://www.tlinesim.com - lossy lines, eye diagrams and much more).
>>> Other people will have different preferences, and it also depends what you
>>> have access to. Note that the tools I mentioned here are all free, so you
>>> don't have to go to your manager to get budget approval to start playing
>>> around with. I just think that starting out simple helps understand the
>>> basic issues before diving into more sophisticated tools (otherwise you
>>> may spend a lot of time and effort in a top-notch tool just to find out
>>> that your model bears little resemblance to real life).
>>>
>>> (3) finally, there are cases when you have to use more sophisticated
>>> tools, but in my experience for most of us that happens less often than
>>> you may think. Of course this is changing when you move to faster and
>>> faster speeds. Also, I believe that understanding of the basic behavior
>>> should come before going to a lot of math (or modeling). Simple tools and
>>> rules of thumb will help you sanity-check any results you get back from
>>> e.g. your high-end 3D simulator. A simple tool combined with good
>>> understanding of your design goes much further than a complicated tool
>>> that you have to trust blindly. E.g. if that full-blown 3D model predicts
>>> 0.01% reflection for the via example above, that would make me highly
>>> suspicious of the result, and I'd immediately go looking for the bug in my
>>> model setup... which wouldn't happen if I had never estimated the rough
>>> effect in the first place.
>>>
>>> Wolfgang
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>> "Joel Brown" <joel@xxxxxxxxxx> <mailto:joel@xxxxxxxxxx>
>>> 01/10/2008 03:43 PM
>>>
>>> To
>>> <wolfgang.maichen@xxxxxxxxxxxx> <mailto:wolfgang.maichen@xxxxxxxxxxxx>,
>>> <Aubrey_Sparkman@xxxxxxxx> <mailto:Aubrey_Sparkman@xxxxxxxx>
>>> cc
>>> <luant@xxxxxxxxxxx> <mailto:luant@xxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
>>> <mailto:si-list@xxxxxxxxxxxxx>,
>>> <si-list-bounce@xxxxxxxxxxxxx> <mailto:si-list-bounce@xxxxxxxxxxxxx>
>>> Subject
>>> RE: [SI-LIST] Re: 50 Ohm Via?
>>>
>>>
>>>
>>>
>>>
>>>
>>> Wolfgang,
>>>
>>> So I crunched some numbers. Assuming a PCB thickness of .09 inches and the
>>> signals travels through the via from top to bottom the prop delay is 7 ps..
>>> 6 times this is 42 ps. The minimum rise time for PCI express gen 1 is 50
>>> ps
>>> so the via impedance should not be a factor. The minimum rise time for gen
>>> 2
>>> is 30 ps so now whether the impedance is a factor is border line. If the
>>> signal only travels half way through, now the prop delay is 3.5 ps for the
>>> signal with a stub length of 3.5 ps. Does this sound right?
>>>
>>> Joel
>>>
>>>
>>> -----Original Message-----
>>> From: si-list-bounce@xxxxxxxxxxxxx <mailto:si-list-bounce@xxxxxxxxxxxxx>
>>> [mailto:si-list-bounce@xxxxxxxxxxxxx]
>>> On
>>> Behalf Of wolfgang.maichen@xxxxxxxxxxxx
>>> <mailto:wolfgang.maichen@xxxxxxxxxxxx>
>>> Sent: Thursday, January 10, 2008 3:09 PM
>>> To: Aubrey_Sparkman@xxxxxxxx <mailto:Aubrey_Sparkman@xxxxxxxx>
>>> Cc: joel@xxxxxxxxxx <mailto:joel@xxxxxxxxxx>; luant@xxxxxxxxxxx
>>> <mailto:luant@xxxxxxxxxxx>; si-list@xxxxxxxxxxxxx
>>> <mailto:si-list@xxxxxxxxxxxxx>;
>>> si-list-bounce@xxxxxxxxxxxxx <mailto:si-list-bounce@xxxxxxxxxxxxx>;
>>> wolfgang.maichen@xxxxxxxxxxxx <mailto:wolfgang.maichen@xxxxxxxxxxxx>
>>> Subject: [SI-LIST] Re: 50 Ohm Via?
>>>
>>> Aubrey,
>>> what I tried to say is, if the transition time through your via (or
>>> through the stub hanging off) is small (rule of thumb < 16/th) of your
>>> signal rise time, then in most cases the impedance of the via structure
>>> does not matter much, and the reflection (and rise time degradation) from
>>> the stub does not matter much (i.e. they have negligiblke influence on
>>> your signal integrity). Of course there are cases when this simple rule
>>> breaks down. E.g. assume a short stub with VERY small clearance to
>>> surrounding planes - this will add a lot of capacitance, so even though
>>> the physical length of the stub may be very short, it's parasitic
>>> capacitance in combination with the transmission line impedance will
>>> create an untolerably large time constant - i.e. a strong reflection, and
>>> strong bandwidth degradation. But in practice such extreme cases are .
>>>
>>> If the via impedance is not 50 Ohms, and the transition time through the
>>> via gets into the order of magnitude of your signal rise time, then you
>>> will see the effects of those reflections. In this case it is necessary to
>>>
>>> get the via transition close to 50 Ohms as well so the reflections are
>>> small.
>>>
>>> Wolfgang
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>> <Aubrey_Sparkman@xxxxxxxx> <mailto:Aubrey_Sparkman@xxxxxxxx>
>>> 01/10/2008 11:56 AM
>>>
>>> To
>>> <wolfgang.maichen@xxxxxxxxxxxx> <mailto:wolfgang.maichen@xxxxxxxxxxxx>,
>>> <joel@xxxxxxxxxx> <mailto:joel@xxxxxxxxxx>
>>> cc
>>> <luant@xxxxxxxxxxx> <mailto:luant@xxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
>>> <mailto:si-list@xxxxxxxxxxxxx>,
>>> <si-list-bounce@xxxxxxxxxxxxx> <mailto:si-list-bounce@xxxxxxxxxxxxx>
>>> Subject
>>> RE: [SI-LIST] Re: 50 Ohm Via?
>>>
>>>
>>>
>>>
>>>
>>>
>>> All,
>>> I have not been paying close attention to this thread, so feel free to
>>> blast me if I'm off base or missed something, but my reaction on what
>>> I've read: If all you have to worry about is the time through the via,
>>> then you probably don't have to worry about the via. My $0.02 on when
>>> you really have to worry about vias is when you do a layer transition
>>> that causes a dangling stub that causes a resonance in your frequencies
>>> of interest. The thicker the board, the lower the frequency.
>>>
>>>
>>> Aubrey Sparkman
>>> Enterprise Engineering Signal Integrity Team
>>> Dell, Inc.
>>> Aubrey_Sparkman@xxxxxxxx <mailto:Aubrey_Sparkman@xxxxxxxx>
>>> (512) 723-3592
>>> "A Measurement for every Model and a Model for every Measurement.
>>> Without Correlation, I don't believe either." - Aubrey Sparkman
>>>
>>>
>>> -----Original Message-----
>>> From: si-list-bounce@xxxxxxxxxxxxx <mailto:si-list-bounce@xxxxxxxxxxxxx>
>>> [mailto:si-list-bounce@xxxxxxxxxxxxx]
>>> On Behalf Of wolfgang.maichen@xxxxxxxxxxxx
>>> <mailto:wolfgang.maichen@xxxxxxxxxxxx>
>>> Sent: Thursday, January 10, 2008 1:02 PM
>>> To: Joel Brown
>>> Cc: luant@xxxxxxxxxxx <mailto:luant@xxxxxxxxxxx>; si-list@xxxxxxxxxxxxx
>>> <mailto:si-list@xxxxxxxxxxxxx>;
>>> si-list-bounce@xxxxxxxxxxxxx <mailto:si-list-bounce@xxxxxxxxxxxxx>;
>>> wolfgang.maichen@xxxxxxxxxxxx <mailto:wolfgang.maichen@xxxxxxxxxxxx>
>>> Subject: [SI-LIST] Re: 50 Ohm Via?
>>>
>>> Joel,
>>> a good estimate for the prop delay is simply
>>>
>>> T_prop = length / (speed_of_light x eps_r)
>>>
>>> where length is the length of the via, speed_of_light is 30cm/ns (or 6
>>> inches/ns) - make sure lengths has the same dimension (cm or inches),
>>> and eps_r is the dielectric constant (2.5 ... 4.5 for typical PCB
>>> materials).
>>> For example, for a board made out of FR-4 (eps_r approx 4), Of course
>>> that does not take into account where the signal traces attach to the
>>> via, on the other hand you wouldn't want to have any stubs hanging off
>>> that are even close to 1/6th of your signal rise time.
>>>
>>> As for loosely vs. closely coupled, that depends. I would NOT recommend
>>> leaving out the return vias simply because you have a closely coupled
>>> differential pair. That would make your design very sensitive to any
>>> common mode component on your signal - causing e.g. excessive EMI. There
>>> have benn quite a few threads on this duscussion list in the past.
>>>
>>> Regards,
>>>
>>> Wolfgang
>>>
>>>
>>>
>>>
>>>
>>>
>>> "Joel Brown" <joel@xxxxxxxxxx> <mailto:joel@xxxxxxxxxx>
>>> 01/09/2008 08:30 PM
>>>
>>> To
>>> <wolfgang.maichen@xxxxxxxxxxxx> <mailto:wolfgang.maichen@xxxxxxxxxxxx>,
>>> <luant@xxxxxxxxxxx> <mailto:luant@xxxxxxxxxxx> cc
>>> <si-list@xxxxxxxxxxxxx> <mailto:si-list@xxxxxxxxxxxxx>,
>>> <si-list-bounce@xxxxxxxxxxxxx> <mailto:si-list-bounce@xxxxxxxxxxxxx> Subject
>>> RE: [SI-LIST] Re: 50 Ohm Via?
>>>
>>>
>>>
>>>
>>>
>>>
>>> Wolfgang,
>>>
>>> Your point about how much simulation is worthwhile is well taken.
>>> I work for a small company and wear a lot of hats, I am not a full time
>>> SI engineer. We do have some tools such as Hyperlynx and Hspice which in
>>> my opinion have been under utilized. I know Hyperlynx claims to have
>>> some GHz via modeling capability but I am not sure how accurate it is
>>> and I don't think it takes the return path such as stitching vias into
>>> account. I have been trying to do more simulation as time allows and
>>> learning along the way.
>>> It's certainly not easy to learn multiple simulation environments and
>>> all the pitfalls. I have yet to get to the point to where I can
>>> correlate measurements against simulations.
>>>
>>> How would I know what the prop delay through a via will be?
>>>
>>> To Chris:
>>>
>>> I have been reading several places that recommend using loosely coupled
>>> differential pairs, that is why I mentioned 50 ohms. I know there are
>>> religious beliefs about tightly coupled vs loosely coupled pairs. The
>>> material I read regarding loosely coupled pairs mentioned advantages
>>> such as wider trace widths for a given impedance and avoiding
>>> degradation of rise time caused by coupling between signals within a
>>> pair.
>>>
>>> Thanks - Joel
>>>
>>>
>>> -----Original Message-----
>>> From: si-list-bounce@xxxxxxxxxxxxx <mailto:si-list-bounce@xxxxxxxxxxxxx>
>>> [mailto:si-list-bounce@xxxxxxxxxxxxx]
>>> On
>>> Behalf Of wolfgang.maichen@xxxxxxxxxxxx
>>> <mailto:wolfgang.maichen@xxxxxxxxxxxx>
>>> Sent: Wednesday, January 09, 2008 7:19 PM
>>> To: luant@xxxxxxxxxxx <mailto:luant@xxxxxxxxxxx>
>>> Cc: si-list@xxxxxxxxxxxxx <mailto:si-list@xxxxxxxxxxxxx>;
>>> si-list-bounce@xxxxxxxxxxxxx <mailto:si-list-bounce@xxxxxxxxxxxxx>
>>> Subject: [SI-LIST] Re: 50 Ohm Via?
>>>
>>> As a simple rule of thumb:
>>> Usually not very important if the prop delay through the via is less
>>> than about 1/6th of your signal rise time (you may be able to get away
>>> with 1/4th). Rise time is much more important than bit rate or clock
>>> frequency.
>>>
>>> As to the number of vias - this can of course aggravate the problem; but
>>> on the other hand, I wouldn't attempt to design a 10 Gb/s channel and
>>> put in more than maybe two vias...
>>>
>>> just my 2 cents
>>>
>>> Wolfgang
>>>
>>>
>>>
>>>
>>>
>>> "Tony Luan" <luant@xxxxxxxxxxx> <mailto:luant@xxxxxxxxxxx>
>>> Sent by: si-list-bounce@xxxxxxxxxxxxx <mailto:si-list-bounce@xxxxxxxxxxxxx>
>>> 01/09/2008 07:06 PM
>>> Please respond to
>>> luant@xxxxxxxxxxx <mailto:luant@xxxxxxxxxxx>
>>>
>>>
>>> To
>>> <si-list@xxxxxxxxxxxxx> <mailto:si-list@xxxxxxxxxxxxx>
>>> cc
>>>
>>> Subject
>>> [SI-LIST] Re: 50 Ohm Via?
>>>
>>>
>>>
>>>
>>>
>>>
>>> How critical the characteristic impedance of via transition is? It
>>> depends on the bit rate, channel insertion loss and the number of vias
>>> on each channel.=20
>>>
>>> BR
>>> Tony
>>>
>>> -----Original Message-----
>>> From: si-list-bounce@xxxxxxxxxxxxx <mailto:si-list-bounce@xxxxxxxxxxxxx>
>>> [mailto:si-list-bounce@xxxxxxxxxxxxx]
>>> On Behalf Of Harry Selfridge
>>> Sent: Wednesday, January 09, 2008 6:50 PM
>>> To: 'SI LIST'
>>> Subject: [SI-LIST] Re: 50 Ohm Via?
>>>
>>> There was an article written about controlled impedance vias several=20
>>> years ago by Thomas Neu of Texas Instruments. I haven't seen any=20
>>> followup articles by anyone on the subject since. You can read Neu's=20
>>> article online at:
>>>
>>> http://www.edn.com/index.asp?layout=3Darticle&articleid=3DCA324403
>>> <http://www.edn.com/index.asp?layout=3Darticle&articleid=3DCA324403> .
>>>
>>> Others may have experienced different results, but I've never found=20
>>> controlled impedance vias to be necessary or useful. The distances=20
>>> involved in a via are so short that any pretense of matching=20
>>> impedance is negligible compared with other variations that you might=20
>>> encounter over the full length of a signal path. One board we built=20
>>> for a customer provided two signal paths, one with Neu's controlled=20
>>> impedance vias, and duplicates without. Testing of the loaded board=20
>>> showed no appreciable difference in performance, and the loss of=20
>>> board space to the structure necessary to achieve the controlled=20
>>> impedance vias was considerable.
>>>
>>> Regards - Harry
>>>
>>> At 05:51 PM 1/9/2008, you wrote:
>>>
>>>
>>>> Is there such a thing as a design methodology for designing a PCB via
>>>>
>>>>
>>> with
>>>
>>>
>>>> 50 ohm impedance, or does it have to be done iteratively using a 3D
>>>>
>>>>
>>> field
>>>
>>>
>>>> solver?
>>>> Are controlled impedance vias necessary, worthwhile or helpful for
>>>> multi-gigabit serial links running at 1 to 5 Gbps?
>>>>
>>>>
>>>>
>>>> Thanks - Joel
>>>>
>>>>
>>>
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>
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To unsubscribe from si-list:
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For help:
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List technical documents are available at:
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or at our remote archives:
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Old (prior to June 6, 2001) list archives are viewable at:
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Other related posts:
- » [SI-LIST] Re: [!! SPAM] Re: Re: 50 Ohm Via?
