[SI-LIST] Re: [SI-LIST]Re:[SI-LIST]Re:HowV-TtablebeenextractedforIBISmodel

  • From: steve weir <weirsi@xxxxxxxxxx>
  • To: ZHENGZHIWEI <zhiweizh@xxxxxxx>
  • Date: Tue, 17 May 2011 01:34:06 -0700

IDEALLY there is no current in the pull-down transistor in the cited 
example because the CORE is driving low, which disables the pull-down 
transistor, and enables the pull-up transistor.  In reality, the V-T 
curves will infer any cross-conduction / crowbarring that may occur as a 
pedestal or double transition.
Steve.

On 5/17/2011 1:21 AM, ZHENGZHIWEI wrote:
>
>  Hello Tom,
>
> Thanks!
>
> But my question is a little bit different:
> In V4 cook book, there has a sample about rising wavefrom terminated 
> to ground. In Page 62.
> "If the signal at the input (â??From Coreâ??) is transitioning from high 
> to low, the output will transition from low to high. Under ideal 
> conditions, no current will flow through the pulldown transistor and 
> the core is driving low"
> I can't understand why there has no current flow through pulldown 
> transistor? And in measurement, how to check if there has current 
> through pulldown transistor, and how to exclude this current if there 
> has? Because I think there has overlap time in Pullup and Pulldown 
> transistors' transition.
>
> thanks a lot for your patient!
> zhiwei
>
> ----- Original Message -----
> From:"Tom Dagostino" <tom@xxxxxxxxxxxxx>
> To: ''steve, weir'', <weirsi@xxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
> Cc:
> Sent:Tue May 17 14:20:25 UTC+0800 2011
> Subject: [SI-LIST] Re: [SI-LIST]Re:HowV-TtablebeenextractedforIBISmodel
> There is no trick to this, it is outlined in the specification and in 
> the cook-book. For a normal totem-pole output you need to make at a 
> minimum 4 VT waveforms per corner, a rising edge terminated to ground, 
> a rising edge terminated to Vdd, a falling edge terminated to ground 
> and a falling waveform terminated to Vdd. You must keep the sets of 
> rising waveforms and the set of falling waveforms time correlated. Any 
> good scope will allow you to make these measurements. You need to make 
> sure you have enough bandwidth in your system to capture the edge 
> rates. You will need to make test fixtures that have very clean RF 
> connections between the IC under test and the external test equipment. 
> You will need to provide clean power to the IC. And you will need to 
> be able to control the IC's temperature and supplied voltage. And if 
> you can get corner silicon measure those ICs at the appropriate 
> conditions.
>
> You will need a word generator that will interface with the IC so that 
> you can control the IC. You will need to be able to stop the outputs 
> so that you can measure the output hi, output low and tri-state/input 
> conditions. You will need to be able to toggle the outputs so that you 
> can make your rising and falling waveform measurements. You will have 
> to write a program to extract all these measurements from the IC. Once 
> you have all the data collected you will need to reduce the data to 
> the IBIS format - another program. And you will have to have an 
> individual test plan/test program for every IC that you model. This is 
> not the days of TTL logic anymore. Most ICs are very specific in their 
> function and need to be controlled/programmed uniquely. The control 
> register section of IC datasheets are getting extremely large and 
> complex these days.
>
> You'll need a dual channel scope with at least 20 GHz bandwidth. A 
> word generator with at least a dozen outputs. You will need at least a 
> half dozen power supplies. Many of today's ICs have many independent 
> power domains. And you will need a curve tracer function for the IV 
> measurements.
>
> Then you will need to be able to measure C_comp and package parasitics 
> so either a TDR plug in for your scope or a good VNA will get you 
> started. Plus the SW to extract that information.
>
> Then you will spend time with your accessories vendors collecting 
> cabling, connectors, attenuators, DC blocks, calibration sets, etc.
>
> Then there are those nice to have things, Zo probes, FET probes, 
> special stimuli, an SI simulator to verify your models, etc.
>
> Tom Dagostino
>
> Teraspeed Labs
> 9999 SW Wilshire St.
> Suite 102
> Portland, OR 97225
> USA
>
> 503-430-1065 Cell
> 971-279-5325 Office
> 971-279-5326 FAX
> tom@xxxxxxxxxxxxx
> www.teraspeed.com
>
> Teraspeed Consulting Group LLC
> 121 North River Drive
> Narragansett, RI 02882
> 401-284-1827
>
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx 
> [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of steve weir
> Sent: Monday, May 16, 2011 6:35 PM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: [SI-LIST]Re:HowV-TtablebeenextractedforIBISmodel
>
> Techniques to generate those tables from measurements have been 
> developed and are used by model development services such as Teraspeed 
> Labs in Portland OR.
>
> Steve.
>
> On 5/16/2011 6:12 PM, ZHENGZHIWEI wrote:
> >
> > Thanks, Aprad!
> > Now here comes another question: how can we get = those VT tables by
> > measurement in lab with a real component? Those transist= ors we can't
> > control it one by one for testing...
> >
> >
> >
> >
> >
> > ----- Original = Message -----
> > From:"Muranyi", "Arpad"
> > To:
> > Cc:
> > Sent:Tue May 17 03:28:52 UTC+0800 2011
> > Subject: [SI-LIS= T] Re:
> > [SI-LIST]Re:[SI-LIST]Re:HowV-TtablebeenextractedforIBISmodel
> > Zhiwei,
> > It looks like you got it right.
> >
> > A falling V-t table = with a pullup will describe how the PD turns ON,
> > A rising V-t table with= a pullup will describe how the PD turns OFF,
> > A rising V-t table with a = puldown will describe how the PU turns ON,
> > A falling V-t table with a pu= ldown will describe how the PU turns OFF.
> >
> >
> > Arpad
> > =3D=3D=3D=3D=
> > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
> > 3D=3D=
> > =3D=3D=3D=3D
> >
> > -----Original Message-----
> > From: si-list-bounce@free= lists.org
> > [mailto:si-list-bounce@xxxxxxxxxxxxx]
> > OnBehalf Of ZHENGZHIWEISent: Sunday, May 15, 2011 9:59 PM
> > To: weirsi@xxxxxxxxxx
> > Cc: si-list= @freelists.org
> > Subject: [SI-LIST] Re: [SI-LIST]Re:[SI-LIST]Re:HowV-Ttabl=
> > ebeenextractedforIBISmodel
> >
> >
> >
> > Hello all,
> > > From reply, seems o= ne VT table account for only one of Pullup and
> > > Pulldown
> > transistor termi= nated to one of rails. And simulator tools will
> > merge affections.
> > For= a falling waveform of VT table terminated to VCC, only account
> > for Pull= down transistor turning on. No Pullup transistor affection
> > included in t= his table, althrough there may have current flow from
> > VCC through PullupandPulldown transistors to ground. The simulation
> > tool will calculate this= part of current from other VT tables(is it
> > the falling wavefrom of VT t= able that terminated to ground? the
> > timing relativeship between them dec= ide how tocaculate).
> > Am I right?
> > thanks!
> > zhiwei
> >
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> --
> Steve Weir
> IPBLOX, LLC
> 150 N. Center St. #211
> Reno, NV 89501
> www.ipblox.com
>
> (775) 299-4236 Business
> (866) 675-4630 Toll-free
> (707) 780-1951 Fax
>
>
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-- 
Steve Weir
IPBLOX, LLC
150 N. Center St. #211
Reno, NV  89501
www.ipblox.com

(775) 299-4236 Business
(866) 675-4630 Toll-free
(707) 780-1951 Fax




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