[SI-LIST] [SI-LIST]: Wired-AND VS Wired-OR logic
- From: Anand.Kuriakose@xxxxxxxxxx
- To: si-list@xxxxxxxxxxxxx
- Date: Wed, 24 Apr 2002 20:25:12 +0630
Hi all,
We can introduce wired-AND logic by connecting 2 or more open-drain (also
open-collector) outputs together with a single pull-up resister. The logic of
AND logic results as follows: If one or more of the drivers asserts the output
to low state (electrically low ), the equivalent output is low, which is how an
AND gate functions. Also the connected signals have to be active-low signals.
I have seen many documents refering to the above scenario as wired-OR logic. It
doesnt make sense. Also the PCI spec 2.2, sec2.1 refers to O/D signals (ex INTX#
and SERR#) as to be capable of introducing wired-OR logic.
So what is wired-OR logic? How do we realise this logic? Does the active level
of the connected signals make the difference?
Also one more question. When it comes to wired-AND logic, only one device can
assert its output low. We cannot have more than one device asserting its output
low simultaneously. Am i right in saying so. If yes, is this allowed in wired-OR
logic.
Thanx in advance for all the valuable inputs.
Regards,
Anand Kuriakose.
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List archives are viewable at:
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
