[SI-LIST] SI project in Santa Clara, CA is still open (all onsite)

From: "Kevin Pierpoint" <kevin_pierpoint@xxxxxxxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Date: Tue, 20 Nov 2007 14:38:51 -0500
Hello guys....I wanted to let you guys know that there is still a
consulting opportunity open for one of my clients in Santa Clara. I have
gotten quite a few responses, so thank you for all of them. But, the
issue has been that my client needs the work to be done onsite. So, I
wanted to run it by everyone one more time to see if anyone could
committ to a 4-6 month project onsite in Santa Clara, CA:
 
seeking a Sr. Signal 
Integrity Engineer. The group provides a dynamic, communicative 
environment offering opportunities for cross training in the areas of 
opto-electric devices, Ethernet PHYs, clock tree distribution and 
jitter measurement and mitigation techniques.
Responsibilities: 

1. Use analytical and simulation tools to generate design guidelines 
and stackups for high-speed boards and multi-gbps backplanes with cost 
and design tradeoffs in consideration.
2. Detailed placement and routing review for boards and backplanes.
3. Post layout simulation on boards as required. 
4. Digital interconnect, packaging, high-speed I/O buffer analysis and 
simulation. Includes accurate timing and voltage margin analysis.
5. Signal integrity measurement and verification in the lab using high 
speed scopes, network and spectrum analyzers, BERT and other test
equipment.
6. Experience with SERDES based interfaces running above 1Gbps and 
DDR/QDR memory and PCI interface would be advantageous. Equal 
Employment Opportunity Employer


Requirements: 

* Proficiency in HSPICE and 3D field solver (CST). 
* Proficiency in ADS or simulating Serdes based designs.
* Proficiency in TDR based equipment and measurement capability. 
* Proficiency in S-parameter modeling and measurement.
* Familiarity with tools like Sigrity, MATLAB. 
* Familiarity with PCB fabrication technology and stackup design. 
* Proficiency in a post-layout simulation tool (HyperLynx GHz). 
* Familiarity with latest time and frequency domain test equipment. 
* Good understanding of ASIC I/O development and high-speed digital 
system design and verification.
* Ideal candidate would have MSEE degree with 5 years or BSEE degree 
with 7 years of relevant experience.

Required Skills: HSpice, ADS, Serdes based designs, TDA IConnect.
 
 

Kevin D. Pierpoint

Branch Manager

Oxford & Associates, Inc.

a division of On Assignment

Software/Hardware Engineering Consulting Services

 

(408) 245-3915 x111 phone

(408) 245-3977 fax

www.oxfordcorp.com <http://www.oxfordcorp.com/>  

The Right Talent. Right Now.(r)

 

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[SI-LIST] SI project in Santa Clara, CA is still open (all onsite)

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