[SI-LIST] SCV EMC May 13th meeting
- From: "hansm" <hans.mellberg@xxxxxxxxxxxx>
- To: <emc-pstc@xxxxxxxxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Mon, 12 May 2003 13:52:29 -0700
Membership not required, All welcome, Bring a collegue
The Santa Clara Valley EMC Society is please to present:
. Tuesday, May 13th, 2003
"Considerations for Advanced EMC Design Flow"
By: Sudip Das
see www.scvemc.org for details and map
Details:
- In an ideal world, every hardware project should have a engineer
responsible for functional design, regulatory compliance, signal integrity
(SI), CAD, and manufacturing. Each of them would get ample time to
thoroughly check and simulate their portions of the design. But in the real
world, we are often faced with a lack of both time and resources. What can
be done to make our design process effective, even in very fast-paced
projects, so that none of the design objectives are overlooked? Another
challenge would be: how to introduce this new process without breaking down
the existing legacy process? And, of course, how and where does EMC fit in
this overall process flow? One approach would be to embed the design
requirements in the CAD tools, and by efficiently designing the schematics
and PCB layout to preserve the compliance and SI knowledge-base from one
project to another.
THE SOCIAL GATHERING WILL BEGIN AT 5:30pm AND THE MEETING WILL BEGIN AT
7:00pm
Hans Mellberg
Engineering Manager
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