Hi experts,
some time ago i asked SI-List about slew rate vs. Rise time..
I just came acros an article from
Aditya Rao
<https://www.signalintegrityjournal.com/authors/422-aditya-rao>, Melinda
Piket-May
<https://www.signalintegrityjournal.com/authors/371-melinda-piket-may>,
and Eric Bogatin
<https://www.signalintegrityjournal.com/authors/25-eric-bogatin> in the
Si Journal:
https://www.signalintegrityjournal.com/articles/2092-bandwidth-of-signals-what-is-important-rise-time-or-slew-rate?pageÿutm_campaignºndwidth+of+Signals%3A+What+is+Important%2C+Rise+Time+or+Slew+Rate%3F&utm_contentÿMLLinkID%3A+7&utm_mediumÿail&utm_sourceÿ_Signal+Integrity+Journal+Weekly+Newsletter
thanks to the authors for this one !!!
but there is still one open question:
What is the impact of slew Rate or Rise time to a silicon receiver
implementation?
JEDEC uses slew rate to define the energy that is driven in to a
receiver and potentially gain from some overdrive with higher voltage
for the parameter how fast a receiver is switching (at least with the
definition of AC/DC levels).
Maybe it anyhow turned out to be the wrong way, as DDR4/5 starts only to
work with masks.
But still ... the faster the reveiver is switching , the less
uncertainty is coming in the RX Timing..
Maybe this still makes sense for a parallel bus ??
From SI point of view rise time is the important parameter .. but for
the Receiver as well ?
any thought are welcome...
Hermann
--
EKH - EyeKnowHow
Signal Quality - Made in Bavaria
Hermann Ruckerbauer
www.EyeKnowHow.de
Hermann.Ruckerbauer@xxxxxxxxxxxxx
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94469 Deggendorf
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