[SI-LIST] Re: Resonance on the pcb board
- From: Graham Kus <nemisonic@xxxxxxxxx>
- To: John Smith <swagguy18@xxxxxxxxx>
- Date: Wed, 6 Apr 2011 19:58:17 -0400
Hi John,
I agree with Tom. At my employer, our experience with resonances at 1GHz -
3GHz has been on various memory systems. If the plane structure has a
half-wave or quarter-wave resonance within the signal bandwidth, then
resonance can be excited by signal activity. We do see this occur on the
DRAM power planes in simulation. This is significantly squelched by adding
decoupling capacitors to the plane structure.
Board resonance:
If you really care about 3.5GHz resonance, is your signal bandwidth 25GHz?
It sounds like you might need to include plane geometry as a concern. I
would say a pragmatic solution is to install bypass capacitors and
distribute them across the plane structure in question. We happen to use 1uF
ceramics for "best capacitance for the cost and size" tradeoffs. There have
been some university studies between disperse and regular patterns.
Basically either solution works. An EM simulation tool can identify resonant
modes and locations. If you are trying to optimize for BOM cost a tool like
Sigrity Optimize PI will identify resonance modes and provide capacitor
placement location while optimizing for capacitor count. Ansys has a
corresponding tool that can get you to the same answer as well.
Signal trace resonance:
Again, I've seen an example of this. In the case where a "T" shaped trace is
required for a CLK/nCLK pair routing from an SoC to two DRAMs, the trace
will behave exactly like a tuning fork. It is important to minimize the
distance of the CLK/nCLK leg between the DRAMs. The initial layout guideline
is to make sure the base leg of the "T" from the SoC is significantly longer
than the top of the "T" between the DRAMs.
Rework options:
If you have a board with mounting holes, add capacitors to the mounting hole
locations to bypass the VDD and VSS planes for the portion of the design
that is impacted by the 3.5GHz resonance. If you have power/gnd vias then
add ceramics to these locations. If you have no bypass capacitors on the
planes then I can say with confidence you are looking a respin because the
design will likely fail at EMC testing.
Additional:
We simulate S-parameters, plane resonance, and power integrity as part of
our design flow before we send the PCB database to fabrication. We initially
got our feet wet by using some consultant firms and then brought some tools
in house after knowing enough to evaluate their cost vs. benefit.
Regards,
Graham Kus
Certified SI Engineer
BSEE
On Thu, Mar 24, 2011 at 10:20 PM, John Smith <swagguy18@xxxxxxxxx> wrote:
> Hi, Experts,
> I am new to signal integrity and I have some questions.
> (1) I did some measurements on my pcb board and found resonances around
> 3.5GHz. Can you give me some hints on what causes the resonances?
> (2) Could you please list some typical issues which can cause resonances
> and
> at what frequency range? I know dielectric loss can cause resonance at
> around 25GHz, what about the other effects?
> Thanks in advance.
>
> Regards,
> John
>
>
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