[SI-LIST] Re: Regarding Pull down
- From: "Adeel Malik" <adeelm@xxxxxxxxxxx>
- To: <bmgman@xxxxxxxxxx>
- Date: Tue, 7 Jan 2003 14:27:04 +0500
Hi Mike,
I wanna ask the question that in normal applications when inputs are
not needed for test reasons, is it OK to tie the un-used inputs of TTL or
NAND devices directly to Ground or one must always need to use the pull-down
resistors.
Regards,
ADEEL MALIK
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Mike Brown
Sent: Sunday, January 05, 2003 1:08 AM
To: deepakkatkoriain@xxxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Regarding Pull down
Deepak,
CMOS and TTL are different things when it comes to pulldown resistors.
First, I assume that the resistors on the inputs are needed for test
reasons, otherwise the inputs could be tied directly to the ground
plane. I'm also going to assume that the trace between the input pin
and the pulldown resistor is relatively short, so that noise pickup
(crosstalk) onto that line is minimal.
The job of the pulldown R is to sink any current (leakage or otherwise)
from the input pin to the ground plane, with a minimum DC drop, to
establish the DC level at that input.
Current must be pulled from a true TTL input to bring it to a low
voltage. This paragraph does not apply to "TTL-compatible" CMOS inputs.
Depending on the particular TTL family, as much as 2 ma might be
required. In any case, this current flows through the pulldown R and
the drop across R limits the low level input voltage at the gate.
Smaller is better in this case, within the limits of the tester's
ability to drive the R to a "1" level.
CMOS does not have the large sink current requirement (a few microamps
at most) so a larger value R may be used as a pulldown, consistent with
a low DC drop across the R.
The amplitude of the ground plane noise, either absolute relative to
some arbitrary point, is not very important with respect to this
discussion. The plane noise at the pulldown resistor ground terminal,
relative to the ground terminal of the gate with the pulled-down input,
appears on that gate input as signal. So long as the noise is less than
the switching threshold of the gate minus the DC drop of the pulldown,
you are in business.
Any crosstalk is superimposed on the gate's DC input level. This is
more of an issue with true TTL than with CMOS inputs, due to the
relatively low Vil spec of TTL and the unavoidable DC drop on its
pulldown R. Thus the "short wire" assumption above.
A numerical example: True TTL with an Iil of 2 mA, with 100 ohm pulldown.
The max drop across the 100 ohms is 200 mV. The threshold is, say, 800
mV. This leaves a minimum noise margin of 600 mV, for coincident ground
and crosstalk noise.
Regards
Mike
Deepak Vinod wrote:
>Hi All,
>I have following simple doudt regarding pull down of
>unused input of CMOS/TTL.
>If my ground plane have 200-300mv (or ideal 0
>volt)noise, then in such case what should be the value
>of pull down resistor for both different family.
>
>I got one feedback, but i am not sure about it.
>He mention that ....
>1) The value should be low (around 100 ohms), so it
>can not pick up the noise and give false trigger to
>input.
>
>what is my doudt is, if R will be low then it will
>consumed more ripple current from plane and generate
>faulty voltage.
>
>What will be the preferable value of R (100 ohms,1K
>ohms, 4.7Kohms)?
>Please reply soon.
>
>Thanks in Anticipation.
>Deepak
><snip>
>
>
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