[SI-LIST] Re: Reference layers for high speed diff pairs

  • From: Ilan Wolff <shchifwork@xxxxxxxxx>
  • To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
  • Date: Thu, 10 Jan 2013 12:15:57 -0800 (PST)

Hi Scott,
 
Thanks for your feedback.
I must admit ther's point in your reply regarding the 3D
solver that I don’t quite follow.
(I might be exposing my ignorance in the next few lines, but
I guess this is the way to learn.)
 
Let’s say I go for the 1 GND & 1 power plane option (#2),
and that on the “system” level PCB the same reference plane scheme is used.
1.       How would the solver be
able to differentiate between the two types of planes?
2.       Up to now I’ve seen 3D
solvers produce sNp files & TDR type simulations, but the reference planes
were always “muted”. Are these solvers capable of producing a sNp file that
would include the non-GND plane as one of the ports? What meaning would it
have, since this plane is clearly not 50ohm?
3.       Is the noise on the power
planes more “dangerous” than noise on the GND planes? (Isn’t that one of 
the
main reasons we have the signal routed as a differential pair)
 
Thanks,
Shchif

________________________________
 From: Scott McMorrow <scott@xxxxxxxxxxxxx>
To: shchifwork@xxxxxxxxx 
Cc: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx> 
Sent: Thursday, January 10, 2013 3:45 PM
Subject: Re: [SI-LIST] Reference layers for high speed diff pairs
 

Ilan

Having modeled, analyzed, designed, measured, and correlated measurements to 
modeling for 16 and 25G packages, you most definitely want to use GND/GND 
referencing.  In fact, the entire stackup should be encapsulated by Gnd layers 
above and below any power layers, so that the first and last thing that a 
signal via sees is a ground layer.  Otherwise, noise injection into the power 
supplies and crosstalk peaking will occur at very inconvenient places that are 
not necessarily localized.

Unless you want to do the 3D package analysis necessary to convince yourself 
that you might be able to use GND/Power referencing, don't do it.

When it comes to the signal path in packages, ground layers, ground vias, and 
ground balls, are good ... and power layers, power vias, and power balls are 
bad.

best regards,

Scott

-- 

Scott McMorrow
Teraspeed Consulting Group LLC
16 Stormy Brook Road 
Falmouth, ME 04105
(401) 284-1827 Business
http://www.teraspeed.com/

Teraspeed® is the registered service mark of
Teraspeed Consulting Group LLC

On Thu, Jan 10, 2013 at 5:56 AM, Ilan Wolff <shchifwork@xxxxxxxxx> wrote:

Hi experts,
>I'm workingon a package design. This chip will have multiple 10G (and up) 
>differential pairs running between the PCB balls & the silicon bumps.
>We are able (in terms of ball-out, bump-out & package layer count) to 
>accommodate the following 2 configurations:
>1.Sandwiching the diff pairs between 2 GND (Analog Vss) layers.
>2. Sandwiching the diff pairs between1 GND (Analog Vss) layer& 1 SERDES supply 
>layer (Tx supply for Tx pairs & Rx supply for Rx pairs).
>
>
>Additional information:
>Both non-GND supplies will have AC decoupling caps underneath the chip, on the 
>PCB, near the supply's vias into the package.
>If using option 2, on the PCB end of the package, each diff pair will have two 
>reference viasof the relevant non-GND supply & (at least) two reference viasof 
>GND.
>
>looking at our past designs we have packages using both options.All of them 
>seem to work well. But now that we're moving on in data rates I'd like to make 
>an informative decision.
>I'm trying to figure out if there is any preference in terms of SI.
>
>Care to voice your opinion?
>
>Many thanks,
>Shchif
>
>
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